Vertical MISFET transistor surrounded by a Schottky barrier diode with a common source and anode electrode

• US 6,707,128 B2
• Filed: 06/10/2002
• Issued: 03/16/2004
• Est. Priority Date: 06/13/2001
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Moriguchi, Kouji, Hokomoto, Yoshitaka
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Mandala, Jr., Victor A.
• Application Number:
  US10/164,633
• Publication Number:
  US 20020190340A1
• Time in Patent Office: 645 Days
• Field of Search: 257/484, 257/486, 257/339, 257/341, 257/483, 257/127, 257/128, 257/130, 257/589, 257/605, 257/328, 257/329, 257/330, 438/138, 438/268, 438/270, 438/570
• US Class Current: 257/484
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type;

a base layer of a second conductivity layer provided in the first semiconductor layer, the base layer defining a vertical MISFET including a plurality of source regions and gate electrodes, each of the gate electrodes being provided on a gate insulation film;

a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer to surround the base layer;

a guard ring region of the second conductivity type provided to surround the SBD-forming region;

a first main electrode disposed above the first semiconductor layer to cover both the SBD-forming region and the source regions, the first main electrode being provided in common as a source electrode of the MISFET and an anode of the SBD;

a surface gate electrode disposed above the first semiconductor layer to be isolated from the first main electrode by an insulation film, the surface gate electrode being electrically connected to the gate electrodes; and

a second main electrode provided in common as both a drain electrode of the MISFET and a cathode of the SBD.

2. The semiconductor device according to claim 1, wherein the SBD-forming region is arranged to surround continuously the base layer.

3. The semiconductor device according to claim 2, wherein the guard ring region is provided to surround the SBD-forming region.

4. The semiconductor device according to claim 2, wherein the first main electrode is provided on a barrier metal via contact holes of the insulation film and comprised of a metal connected to the source regions and the base layer.

5. The semiconductor device according to claim 4, wherein the barrier metal is continuously provided on part of the guard ring regions, on part of the surface of the source regions through the contact holes formed in the insulation film, and on part of the surface of the base layer.

6. The semiconductor device according to claim 2, wherein the second main electrode is provided over an opposite surface of the semiconductor substrate.

7. The semiconductor device according to claim 2, further comprising a plurality of terminated guard ring regions, provided at predetermined intervals in the first semiconductor layer of the SBD-forming region, having the second conductivity type.

8. The semiconductor device according to claim 7, wherein a conductor having the second conductivity type is buried in each of trenches selectively formed at predetermined intervals to provide the terminated guard ring regions.

9. The semiconductor device according to claim 2, wherein the surface gate electrode is provided above the first semiconductor layer within a region surrounded by the guard ring region.

10. The semiconductor device according to claim 2, wherein the gate electrode is a trench gate electrode buried in a gate trench covered with the gate insulation film, the gate trench being formed down to the first semiconductor layer from the surface of the source regions through the base layer.

11. The semiconductor device according to claim 1, wherein the SBD-forming region is arranged to surround intermittently the base layer.

12. The semiconductor device according to claim 11, wherein the guard ring region is provided to surround the SBD-forming region.

13. The semiconductor device according to claim 11, wherein the first main electrode is provided on a barrier metal via contact holes of the insulation film and comprised of a metal connected to the source regions and the base layer.

14. The semiconductor device according to claim 13, wherein the barrier metal is continuously provided on part of the guard ring region, on part of the surface of the source regions through the contact holes formed in the insulation film, and on part of the surface of the base layer.

15. The semiconductor device according to claim 11, wherein the second main electrode is provided over an opposite surface of the semiconductor substrate.

16. The semiconductor device according to claim 11, further comprising a plurality of terminated guard ring regions, provided at predetermined intervals in the first semiconductor layer of the SBD-forming region, having the second conductivity type.

17. The semiconductor device according to claim 16, wherein a conductor having the second conductivity type is buried in each of trenches selectively formed at predetermined intervals to provide the terminated guard ring regions.

18. The semiconductor device according to claim 11, wherein the surface gate electrode is provided above the first semiconductor layer within a region surrounded by the guard ring region.

19. The semiconductor device according to claim 11, wherein the gate electrode is a trench gate electrode buried in a gate trench covered with the gate insulation film, the gate trench being formed down to the first semiconductor layer from the surface of the source regions through the base layer.

20. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type;

a base layer of a second conductivity layer provided in the first semiconductor layer, the base layer defining a vertical MISFET including a plurality of source regions and a gate electrode provided on a gate insulation film;

a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer;

a guard ring region of the second conductivity type provided around the SBD-forming region;

a first main electrode disposed above the first semiconductor layer to cover both the SBD-forming region and the source regions, the first main electrode being provided in common as a source electrode of the MISFET and an anode of the SBD;

a surface gate electrode disposed above the first semiconductor layer to be isolated from the first main electrode by an insulation film, the surface gate electrode being electrically connected to the gate electrodes; and

a second main electrode provided in common as both a drain electrode of the MISFET and a cathode of the SBD,

wherein the SBD-forming region is arranged to surround intermittently the base layer.

21. The semiconductor device according to claim 20, wherein the guard ring region is provided to surround the SBD-forming region.

22. The semiconductor device according to claim 20, wherein the first main electrode is provided on a barrier metal via contact holes of the insulation film and comprised of a metal connected to the source regions and the base layer.

23. The semiconductor device according to claim 22, wherein the barrier metal is continuously provided on part of the guard ring region, on part of the surface of the source regions through the contact holes formed in the insulation film, and on part of the surface of the base layer.

24. The semiconductor device according to claim 20, wherein the second main electrode is provided over an opposite surface of the semiconductor substrate.

25. The semiconductor device according to claim 20, further comprising a plurality of terminated guard ring regions, provided at predetermined intervals in the first semiconductor layer of the SBD-forming region, having the second conductivity type.

26. The semiconductor device according to claim 25, wherein a conductor having the second conductivity type is buried in each of trenches selectively formed at predetermined intervals to provide the terminated guard ring regions.

27. The semiconductor device according to claim 20, wherein the surface gate electrode is provided above the first semiconductor layer within a region surrounded by the guard ring region.

28. The semiconductor device according to claim 20, wherein the gate electrode is a trench gate electrode buried in a gate trench covered with the gate insulation film, the gate trench being formed down to the first semiconductor layer from the surface of the source regions through the base layer.