Arrayable, scaleable, and stackable molded package configuration

• US 6,707,140 B1
• Filed: 05/09/2000
• Issued: 03/16/2004
• Est. Priority Date: 05/09/2000
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Deane, Peter, Nguyen, Luu, Tsay, Chen-Hui, Murray, Cade
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/568,558
• Time in Patent Office: 1,407 Days
• Field of Search: 257/686, 257/777, 257/778, 257/723, 257/675, 257/678
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/0219 : Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/0715 : provided by an outer layer of PCB
• CPC Class Codes: H05K 2201/09236 : Parallel layout
• CPC Class Codes: H05K 2201/10121 : Optical component, e.g. opto-electronic component
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A stacked molded package comprising a semiconductor package attached to an electronic device. The semiconductor package includes a semiconductor die which is connected to a set of wire leads and is encapsulated within a protective molding material. Additionally, solder bumps within the molding material are attached to input and output contact points on the semiconductor die. Portions of the solder bumps are exposed through the surface of the molding material so that contact can be made with the electrical contacts of an electronic device to be stacked upon the semiconductor package. The electronic device may be, for example, another semiconductor die or an opto-electronic transceiver. The present invention also includes a method for manufacturing the stacked molded package. The method involves forming the semiconductor package within a molding chamber which is injected with the protective molding material. The method further involves lowering the top surface of the molding chamber onto the solder bumps of the semiconductor package. The contact between the top surface of the molding chamber and the solder bumps flattens a portion of the solder bumps and prevents the flattened portion from being covered with molding material. Manufacturing the semiconductor package may be performed with the current manufacturing infrastructure which is used to make semiconductor packages according to specific form factors. A stacked package is formed when an electronic device is attached to the molded package.

Claims

1. A semiconductor device comprising:

a first semiconductor die having a surface that has a first and a second input/output pad;

a first electrical contact formed on the first input/output pad, the first electrical contact being a solder ball and having a contact surface;

an interconnecting wire having a first and a second end, the first end being wirebonded to the second input/output pad; and

a molding material covering the interconnecting wire, and at least part of the first die and the first electrical contact such that the contact surface of the first electrical contact is exposed through and is flat and flush with a ton surface of the molding material.

2. The semiconductor device as recited in claim 1 further comprising:

a second device; and

a second electrical contact formed on a surface of the second device, the second electrical contact being configured to be placed in electrical connection with the contact surface of the first electrical contact.

3. The semiconductor device as recited in claim 2 wherein:

the second device is a second semiconductor die; and

the second electrical contact is a solder bump.

4. The semiconductor device as recited in claim 2 wherein the second device is an optical device.

5. The semiconductor device as recited in claim 1 wherein the semiconductor device is formed according a form factor selected from the group consisting of Small Outline Package, Quad Flatpack, Leaded Chip Carrier, Dual In-Line Package, Pin Grid Array, Ball Grid Array, and Chip Sized Package.

6. The semiconductor device as recited in claim 1 wherein the first electrical contact is a compressed solder bump.

7. The semiconductor device as recited in claim 1 further comprising a wire lead, the wire lead being electrically connected to the semiconductor die wherein the second end of the interconnecting wire is attached to the wire lead, the wire lead being partially covered by the molding material.

8. The semiconductor device as recited in claim 1 wherein the first die is attached to a die attach pad and the die attach pad being at least partially covered by the molding material.

9. The semiconductor device as recited in claim 2 further comprising a thermal solder ball formed between the first die and the second device so to facilitate the heat transfer between the first die and the second device.

10. The semiconductor device as recited in claim 2 further comprising an underfill material formed between the first die and the second device.

11. The semiconductor device as recited in claim 1 further comprising a heat slug which is attached to the first die, the molding material covering at least part of the heat slug.

12. The semiconductor device as recited in claim 1 further comprising a heat slug which is completely covered by the molding material.

13. The semiconductor device as recited in claim 2 further comprising a heat sink which is attached to the second device.

14. The semiconductor device as recited in claim 1 further comprising a plurality of the first electrical contacts formed on the surface of the first die, each of the plurality of the first electrical contacts having a contact surface, the molding material substantially covering each of the plurality of the first electrical contacts such that the contact surface of each of the first electrical contacts are not covered.

15. The semiconductor device as recited in claim 14, wherein the plurality of the first electrical contacts are located along a perimeter of the first die.

16. The semiconductor device as recited in claim 14 wherein the plurality of the first electrical contacts are formed in an array on the surface of the first die.

17. The semiconductor device as recited in claim 14 further comprising:

a second device; and

a plurality of second electrical contacts formed on a surface of the second device, each of the second electrical contacts being configured to be placed in electrical connection with a contact surface of each of the first electrical contacts.

18. A semiconductor device as recited in claim 1 wherein the flat and flush contact surface of the first electrical contact is made by compressing the first electrical contact with the ton surface of the molding chamber.

19. A semiconductor device package comprising:

a first semiconductor die having a top surface;

a plurality of solder balls attached to the top surface of the first semiconductor die;

a plurality of electrically conductive leads;

a plurality of interconnecting wires that each have a first end and a second end, the first end of each wire being attached to the top surface of the first semiconductor die and the second end of each wire being attached to a respective lead; and

a molding material block having a top surface and a bottom surface, the block completely encapsulating the first semiconductor die and each of the wires, the block also partially encapsulating each of the solder balls and the leads such that each of the solder balls are exposed through the top surface of the block, wherein the portions of the solder balls that are exposed through the block are flat and flush with the too surface of the molding material block.

20. A semiconductor device package as recited in claim 19 wherein each of the leads are exposed through the bottom surface of the block.

21. A semiconductor device package as recited in claim 20 wherein the portions of the leads that are exposed through the block are flat and flush with the bottom surface of the block.

22. A semiconductor device package as recited in claim 19 wherein the solder balls are electrically separated from the wires.

23. A semiconductor device package as recited in claim 19 further comprising:

an external device that is electrically connected to the semiconductor device package through the solder balls that are exposed through the top surface of the block.

24. A semiconductor device package as recited in claim 23 wherein the external device is an optical device.

25. A semiconductor device package as recited in claim 23 further comprising:

a printed circuit board that is electrically connected to the semiconductor device package through the leads.

26. A semiconductor device package as recited in claim 19 further comprising:

a plurality of solder pads formed on the top surface of the first semiconductor die, each of the solder balls being formed on top of a respective solder pad such that each solder ball is attached to the first semiconductor die via one of the solder pads; and

a plurality of wirebond pads formed on the top surface of the first semiconductor die, each of the first ends of each wire being attached to the top surface of the first semiconductor die via respective wirebond pads.

27. A semiconductor device package as recited in claim 21 wherein each of the leads are also exposed through a respective side surface of the molding material block and wherein each of the leads are only exposed through the bottom and a respective side surface of the block.

28. A semiconductor device package as recited in claim 21 wherein each of the leads are only exposed through the bottom surface of the block.