Shielded semiconductor package with single-sided substrate and method for making the same

• US 6,707,168 B1
• Filed: 05/04/2001
• Issued: 03/16/2004
• Est. Priority Date: 05/04/2001
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Hoffman, Paul, Mathews, Doug
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): CRUZ, LOURDES C
• Application Number:
  US09/848,932
• Time in Patent Office: 1,047 Days
• Field of Search: 257/704, 257/796, 361/719, 361/720, 361/816, 361/818, 174/52.1, 174/52.2, 174/52.3, 174/52.4, 174/35.R
• US Class Current: 257/796
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor chip package is disclosed. The package includes a substrate, a metallization layer formed on one side of the substrate and a semiconductor die mounted on the substrate. The semiconductor die is electrically connected to a portion of the metallization layer. A shield element is mounted on the substrate and electrically connected to a portion of the metallization layer. A package mold surrounds the semiconductor die and the shield element

Claims

1. A semiconductor chip package comprising:

a substrate;

a metallization layer formed on one side of the substrate, wherein the metallization layer comprises a plurality of bond fingers;

a semiconductor die mounted on the substrate, the semiconductor die being electrically connected at least some of the bond fingers;

a shield element mounted on the substrate, wherein the shield element is electrically attached to at least one of the bond fingers; and

a package mold surrounding the semiconductor die and the shield element.

2. The semiconductor chip package of claim 1, wherein the metallization layer comprises:

a die pad formed on the substrate;

wherein the semiconductor die is attached to the die pad.

3. The semiconductor chip package of claim 2, further comprising a bond wire forming an electrical connection between a bond pad on the semiconductor die and one of the bond fingers.

4. The semiconductor chip package of claim 1, wherein the shield element comprises:

a substantially planar top surface; and

a plurality of substantially planar side surfaces, the side surfaces being joined to the top surface and to each other with rounded corners.

5. The semiconductor chip package of claim 1, wherein the shield element comprises:

a horizontal top surface; and

at least one vertical side surface, the side surface being joined to the top surface with a rounded corner.

6. The semiconductor chip package of claim 5 wherein the shield element comprises a plurality of openings formed in the top and side surfaces.

7. The semiconductor chip package of claim 5 wherein the top surface of the shield element is circular in shape.

8. The semiconductor chip package of claim 1, wherein the shield element comprises a plurality of legs attached to a corresponding plurality of the bond fingers.

9. The semiconductor chip package of claim 1, wherein at least one the legs of the shield element comprises a concave lower surface shaped to receive a corresponding one of the bond fingers.

10. The semiconductor chip package of claim 1, wherein at least one of the legs of the shield element comprises a convex lower surface, and wherein a corresponding one of the bond fingers comprises a concave upper surface shaped to receive the convex lower surface of the leg.

11. A shielded semiconductor device package comprising:

a substrate having a metallization pattern formed on one side of the substrate, the metallization pattern having a plurality of solderable surface mount pads;

a semiconductor device electrically attached to the metallization pattern and mechanically attached to the substrate;

a metal screen enclosing the semiconductor device and electrically and mechanically attached to a portion of the metallization pattern to shield the semiconductor device from radio frequency energy, wherein the metallization pattern comprises a plurality of bond fingers formed on the substrate and the metal screen is electrically attached to at least one of the bond fingers; and

an insulating material transfer molded about the semiconductor device and encapsulating the metal screen.

12. The shielded semiconductor device package of claim 11, wherein the metallization pattern comprises:

a die pad formed on the substrate; and

wherein the semiconductor die is attached to the die pad.

13. The shielded semiconductor device package of claim 11, wherein the metal screen comprises:

a substantially planar top surface; and

a plurality of substantially planar side surfaces, the side surfaces being joined to the top surface and to each other with rounded corners.

14. The shielded semiconductor device package of claim 11, further comprising solder balls disposed on a side of the substrate opposite the metallization pattern and electrically coupled to the metallization pattern through the substrate.

15. The shielded semiconductor device package of claim 11, further comprising solder balls disposed on a same side of the substrate as the metallization pattern and electrically coupled to the metallization pattern.

16. The shielded semiconductor device package of claim 11, the metal screen comprises a plurality of legs electrically attached to a corresponding plurality of the bond fingers.

17. The shielded semiconductor chip package of claim 16 wherein at least one of the legs of the metal screen comprises a concave lower surface shaped to receive a corresponding bond finger.

18. The shielded semiconductor chip package of claim 16 wherein at least one of the legs of the metal screen comprises a convex lower surface, and wherein a corresponding bond finger comprises a concave upper surface shaped to receive the convex lower surface of the leg.

19. A semiconductor chip package comprising:

a substrate having first and second sides;

a metallization layer formed the first side of the substrate only, with no metallization layer being formed on the second side of the substrate, wherein the metallization layer comprises a plurality of bond fingers;

a semiconductor die mounted on the substrate, the semiconductor die being electrically connected to a portion of the metallization layer;

a shield element mounted on the substrate, wherein the shield element is electrically attached to at least one of the bond fingers.

20. The semiconductor chip package of claim 19, wherein the metallization layer comprises:

a die pad formed on the substrate; and

wherein the semiconductor die is attached to the die pad.

21. The semiconductor chip package of claim 19, further comprising solder balls disposed on the first side of the substrate and electrically coupled to the metallization pattern.