Sequential burst mode activation circuit

• US 6,707,264 B2
• Filed: 11/19/2002
• Issued: 03/16/2004
• Est. Priority Date: 01/09/2001
• Status: Expired due to Fees

• Current Assignee: 2micro International Limited
• Original Assignee: 2micro International Limited
• Inventors: Chang, Yu-Cheng, Yao, Bingwei, Lin, Yung-Lin
• Primary Examiner(s): Clinger, James
• Assistant Examiner(s): Tran, Chuc
• Application Number:
  US10/299,206
• Publication Number:
  US 20030071586A1
• Time in Patent Office: 483 Days
• Field of Search: 315/307, 315/247, 315/225, 315/160, 315/127, 315/119, 315/175, 315/128, 315/219, 315/224, 315/209.R, 315/308, 315/291
• US Class Current: 315/307
• CPC Class Codes: H02J 1/14 Balancing the load in a network
• CPC Class Codes: H02M 1/008 Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H05B 41/3927 by pulse width modulation H05B41/3922 takes precedence

Abstract

A sequential burst mode regulation system to deliver power to a plurality of loads. In the exemplary embodiments, the system of the present invention generates a plurality of phased pulse width modulated signals from a single pulse width modulated signal, where each of the phased signals regulates power to a respective load. Exemplary circuitry includes a PWM signal generator, and a phase delay array that receives a PWM signal and generates a plurality of phased PWM signals which are used to regulate power to respective loads. A frequency selector circuit can be provided that sets the frequency of the PWM signal using a fixed or variable frequency reference signal.

Claims

1. A phased load regulation system comprising a phased delay array adapted to generate a plurality of phase-shifted burst mode signals, wherein each said phase shifted burst mode signal regulating power to a respective load.

2. A phased load regulation system as claimed in claim 1, further comprising a modulator generating a PWM signal, said phased delay array receiving said PWM signal and wherein power delivered to each respective load determined by the pulse width of said PWM signal.

3. A phased load regulation system as claimed in claim 1, further comprising a frequency selector receiving a reference signal and generating a frequency selection signal based on said reference signal, wherein said phased delay array receiving said frequency selection signal and setting the frequency of said phase-shifted burst mode signals based on said frequency selection signal.

4. A phased load regulation system as claimed in claim 2, wherein said modulator further comprising a variable selector for setting the pulse width of said PWM signal.

5. A phased load regulation system as claimed in claim 1, wherein each said load comprises a CCFL.

6. A phased load regulation system as claimed in claim 1, further comprising phase array driver circuits receiving said plurality of phase-shifted burst mode signals and generating at least one power regulating signal for each respective load.

7. A Phased load regulation system as claimed in claim 6, further comprising a half bridge inverter circuit receiving said at least one power regulating signals and generating an AC signal based thereon to power said load.

8. A phased load regulation system as claimed in claim 6, further comprising a full bridge inverter circuit receiving said at least one power regulating signals and generating an AC signal based thereon to power said load.

9. A computer system comprising an LCD panel, a plurality of cold cathode fluorescent lamps lighting said LCD panel, and a lamp driving system comprising a phased delay array adapted to generate a plurality of phase-shifted burst mode signals, wherein each said phase shifted burst mode signal regulating power to each of said plurality of said cold cathode fluorescent lamps.

10. A computer system as claimed in claims 9, further comprising a modulator generating a PWM signal, said phased delay array receiving said PWM signal and wherein power delivered to each respective cold cathode fluorescent lamp determined by the pulse width of said PWM signal.

11. A computer system as claimed in claim 9, further comprising a frequency selector receiving a reference signal and generating a frequency selection signal based on said reference signal, wherein said phased delay array receiving said frequency selection signal and setting the frequency of said phase-shifted burst mode signals based on said frequency selection signal.

12. A computer system as claimed in claim 10, wherein said modulator further comprising a variable selector for setting the pulse width of said PWM signal, thereby setting the brightness of each said cold cathode fluorescent lamp.

13. A computer system as claimed in claim 9, further comprising phase array driver circuits receiving said plurality of phase-shifted burst mode signals and generating at least one power regulating signal for each respective load.

14. A computer system as claimed in claim 13, further comprising a half bridge inverter circuit receiving said at least one power regulating signal and generating an AC signal based thereon to power said load.

15. A computer system as claimed in claim 13, further comprising a frill bridge inverter circuit receiving said at least one power regulating signal and generating an AC signal based thereon to power said load.

16. An LCD panel comprising a plurality of cold cathode fluorescent lamps lighting said LCD panel, and a lamp driving system comprising a phased delay array adapted to generate a plurality of phase-shifted burst mode signals, wherein each said phase shifted burst mode signal regulating power to each of said plurality of said cold cathode fluorescent lamps.

17. An LCD panel as claimed in claim 16, further comprising a modulator generating a PWM signal, said phased delay array receiving said PWM signal and wherein power delivered to each respective cold cathode fluorescent Lamp determined by the pulse width of said PWM signal.

18. An LCD panel as claimed in claim 16, further comprising a frequency selector receiving a reference signal and generating a frequency selection signal based on said reference signal, wherein said phased delay array receiving said frequency selection signal and setting the frequency of said phase-shifted burst mode signals based on said frequency selection signal.

19. An LCD panel as claimed in claim 17, wherein said modulator further comprising a variable selector for setting the pulse width of said PWM signal, thereby setting the brightness of each said cold cathode fluorescent lamp.

20. An LCD panel as claimed in claim 16, further comprising phase array driver circuits receiving said plurality of phase-shifted burst mode signals and generating at least one power regulating signal for each respective load.

21. An LCD panel as claimed in claim 20, further comprising a half bridge inverter circuit receiving at least one said power regulating signal and generating an AC signal based thereon to power said load.

22. An LCD panel as claimed in claim 20, further comprising a full bridge inverter circuit receiving said at least one power regulating signal and generating an AC signal based thereon to power said load.