Data normalization technique

• US 6,707,463 B1
• Filed: 07/06/2000
• Issued: 03/16/2004
• Est. Priority Date: 04/30/1997
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Amies, Christopher, Gibson, Ian
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/611,978
• Time in Patent Office: 1,349 Days
• Field of Search: 345/501, 345/433, 345/561-563, 345/619
• US Class Current: 345/619
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

A graphics processor performs graphical operations on graphical objects represented in an external data format. The graphics processor includes a setup unit, first and second mapping units, and a calculator. The setup unit sets up one or more registers reflecting a current instruction. The first mapping unit maps, responsive to the current instruction, the external data format to at least one corresponding internal data format selected from a set of internal data formats. The calculator performs graphical operations on the graphical objects when in one of the selected internal data formats. The second mapping unit maps, responsive to the current instruction, each internal data format in the set of internal data formats to the external data format after the graphical operations have been performed.

Claims

1. A graphics processor for performing graphical operations on graphical objects, the graphical objects being represented in an external data format, said graphics processor comprising:

a setup unit adapted to set up one or more registers reflecting a current instruction;

a first mapping unit adapted to map, responsive to the current instruction, the external data format to corresponding at least one internal data format selected from a set of internal data formats;

a calculator for performing graphical operations on the graphical objects when in said at least one internal data format; and

a second mapping unit adapted to map, responsive to the current instruction, each internal data format in the set of internal data formats to the external data format after the graphical operations have been performed.

2. A graphics processor according to claim 1, wherein said first mapping unit is adapted to select an internal format in response to contents of one or more of the registers.

3. A graphics processor according to claim 1, wherein said second mapping unit is adapted to select an external format in response to contents of one or more of the registers.

4. A graphics processor according to claim 1, wherein the set of internal data formats includes a continuous stream of data of up to four channels per data quantum.

5. A graphics processor according to claim 4, wherein each of the four channels includes at least one of 1-, 2-, 4-, 8-, and 16-bit samples.

6. A graphics processor according to claim 1, wherein the set of internal data formats includes an unpacked bit stream format comprised of a sequence of words, with each word including a predetermined number of valid bits.

7. A graphics processor according to claim 1, wherein the set of internal data formats includes a 32-bit word format, in which each 32-bit word is comprised of four active-byte channels.

8. A graphics processor according to claim 1, wherein the set of internal data formats includes an unpacked byte, 32-bit word format, in which each 32-bit word is comprised of one active-byte channel.

9. A graphics processor according to claim 1, wherein said first and second mapping units are each configured to perform at least one of a byte substitution mapping operation, a byte lane-swapping mapping operation, and a data replication mapping operation.

10. A graphics processor according to claim 1, wherein said first and second mapping units are configured to perform mapping operations on multiple data channels simultaneously.

11. A graphics processor according to claim 1, wherein said first and second mapping units are provided with mapping instructions from a central processing unit associated with said graphics processor.

12. A graphics processor for performing graphical operations on graphical objects, the graphical objects being represented in an external data format selected from a set thereof, said graphics processor comprising:

a setup unit adapted to set up one or more registers reflecting a current instruction;

a first mapping unit adapted to map, responsive to the current instruction, two or more groups of different ones of the set of external data formats to a corresponding internal data format;

a calculator for performing graphical operations on the graphical objects when in the internal data format; and

a second mapping unit adapted to map, responsive to the current instruction, the internal data format to an external data format selected from the set of external data formats after the graphical operations have been performed.

13. A graphics processor according to claim 12, wherein said first mapping unit is adapted to select an external data format in response to contents of one or more of the registers.

14. A graphics processor according to claim 12, wherein said second mapping unit is adapted to select an external data format in response to contents of one or more of the registers.

15. A graphics processor according to claim 12, wherein the set of external data formats includes a continuous stream of data of up to four channels per data quantum.

16. A graphics processor according to claim 15, wherein each of the four channels includes at least one of 1-, 2-, 4-, 8-, and 16-bit samples.

17. A graphics processor according to claim 12, wherein the set of external data formats includes an unpacked bit stream format comprised of a sequence of words, with each word including a predetermined number of valid bits.

18. A graphics processor according to claim 12, wherein the set of external data formats includes a 32-bit word format, in which each 32-bit word is comprised of four active-byte channels.

19. A graphics processor according to claim 12, wherein the set of external data formats includes an unpacked byte, 32-bit word format, in which each 32-bit word is comprised of one active-byte channel.

20. A graphics processor according to claim 12, wherein said first and second mapping units are each configured to perform at least one of a byte substitution mapping operation, a byte lane-swapping mapping operation, and a data replication mapping operation.

21. A graphics processor according to claim 12, wherein said first and second mapping units are configured to perform mapping operations on multiple data channels simultaneously.

22. A graphics processor according to claim 12, wherein said first and second mapping units are provided with mapping instructions from a central processing unit associated with said graphics processor.