Dual memory cell

• US 6,707,698 B2
• Filed: 02/19/2003
• Issued: 03/16/2004
• Est. Priority Date: 10/31/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/371,022
• Publication Number:
  US 20030161175A1
• Time in Patent Office: 391 Days
• Field of Search: 365/105, 365/51, 365/225.7, 365/63
• US Class Current: 365/105
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A memory cell has a first and second conductor. The first conductor is oriented in a first direction and the second conductor is oriented in a second direction. The first conductor has at least one edge. A state-change layer is disposed on the first conductor and a control element is partially offset over the at least one edge of the first conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling or dielectric rupture anti-fuse. A memory array can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array.

Claims

1. A dual memory cell, comprising:

a first conductor having a first surface;

a first state-change element disposed on the first surface;

a first control element disposed on the first state-change element;

a second conductor connected to the first control element, the second conductor having a second surface;

a second state-change element disposed on the second surface;

a second control element disposed on the second state-change element; and

a third conductor parallel to the first conductor connected to the second controlling device.

2. A dual memory cell on a substrate, comprising:

a first conductor disposed on the substrate having an first surface with at least one edge;

a first state-change element disposed over the first surface;

a first control element disposed partially on the first state-change element and partially on the substrate and further disposed over the at least one edge of the first surface;

a second conductor connected to the first control element, the second conductor having a second surface with at least one edge;

a second state-change element disposed over the second surface;

a second control element disposed partially on the second state-change element and further disposed over the at least one edge of the second conductor; and

a third conductor parallel to the first conductor connected to the second controlling device.

3. A dual memory cell on a substrate, comprising:

a first conductor disposed on the substrate having an exposed surface with at least one edge;

a first state-change element disposed on the exposed surface of the first conductor;

a first control element disposed partially on the first state-change element and partially on the substrate and further disposed over the at least one edge of the first conductor;

a first dielectric layer surrounding the first control element;

a second conductor connected to the first control element, the second conductor having an exposed surface with at least one edge;

a second state-change element disposed on the exposed surface of the second conductor;

a second control element disposed partially on the second state-change element and partially on the first dielectric layer and further disposed over the at least one edge of the second conductor;

a second dielectric layer surrounding the second control element; and

a third conductor parallel to the first conductor connected to the second controlling device and disposed further on the second dielectric layer.

4. A dual memory cell, comprising;

a first conductor having a first edge and a second edge;

a second conductor;

a third conductor parallel to the second conductor;

a state-change element disposed over the first conductor including the first and second edges;

a first control element disposed between the first edge and the second conductor and coupled to the state-change element; and

a second control element disposed between the second edge and the third conductor and coupled to the state-change element.

5. A dual memory cell, comprising:

a first conductor;

a second conductor parallel to the first conductor;

a third conductor disposed between the first and second conductors;

a first state-change element disposed on the first conductor;

a second state-change element disposed on the third conductor;

a first control element connected to the first state-change element and the second conductor; and

a second control element connected to the second state-change element and the third conductor.

6. The dual memory cell of claim 5 wherein the first control element is disposed partially on the first state-change element.

7. The dual memory cell of claim 5 wherein the second control element is disposed partially on the second state-change element.

8. A method of making a memory cell on a substrate, comprising the steps of:

creating a first electrode having at least one edge on the substrate;

creating a first state-change layer;

creating a first control element that is disposed over the at least one edge of the first electrode and partially over the first electrode and offset partially beyond the at least one edge of the first electrode;

depositing a first dielectric layer over the processed substrate;

planarizing the deposited dielectric layer;

creating a second electrode having at least one edge, the second electrode orthogonal to the first electrode;

creating a second state-change layer;

creating a second control element that is disposed over the at least one edge of the second electrode and partially over the second electrode and offset partially beyond the at least one edge of the second electrode; and

depositing a second dielectric layer over the processed substrate.

9. The method of claim 8 wherein the step of creating a second state-change layer comprises oxidizing the second electrode.

10. The method of claim 8 wherein the step of creating a second state-change layer comprises depositing a phase-change material.

11. The method of claim 8, further comprising the steps of:

planarizing the deposited dielectric layer; and

creating a third electrode parallel to the first electrode.