Tag design for cache access with redundant-form address

• US 6,707,752 B2
• Filed: 06/22/2001
• Issued: 03/16/2004
• Est. Priority Date: 06/22/2001
• Status: Expired due to Term

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Zhang, Kevin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US09/887,870
• Publication Number:
  US 20020196676A1
• Time in Patent Office: 998 Days
• Field of Search: 365/200, 365/230.03, 365/230.04, 365/230.06
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory and method for accessing data in a memory which uses non redundant-form address decoders is disclosed. Lines in subarrays of the memory are selected using the redundant-form addresses. The least significant bit of the non redundant-form address is used to select between these lines. The compare function of the cache memory is then done with a non redundant-form address.

Claims

1. A memory comprising:

a first and a second array;

redundant-form address decoders coupled to the first and second arrays, correspondingly, for selecting a word line in each of the first and second arrays;

a circuit for selecting between the selected word lines in the first and second arrays based on at least one bit of a non redundant-form memory address.

2. The memory defined by claim 1 wherein the one bit of the non redundant-form memory address is the least significant bit of the address.

3. The memory defined by claim 1 wherein data from the first and second memory arrays are coupled to common lines.

4. The memory defined by claim 1 wherein the circuit for selecting between the selected lines includes first and second sense amplifiers wherein one of the first and second sense amplifiers are activated by the one bit of the non redundant-form memory address.

5. The memory defined by claim 4 wherein the one bit of the non redundant-form memory address is the least significant bit of the address.

6. The memory defined by claim 5 wherein data from the first and second memory arrays are coupled to common lines.

7. The memory defined by claim 6 including a comparator coupled to receive signals from the first and second sense amplifiers and coupled to receive bits of the non redundant-form memory address.

8. The memory defined by claim 7 wherein the comparator provides a hit/miss signal.

9. The memory defined by claim 1 including a comparator for receiving signals from the sense amplifiers and coupled to receive non redundant-form address bits.

10. A memory comprising:

a storage array separated into at least two subarrays;

redundant-form decoders for selecting at least one word line in each of the subarrays in response to redundant-form address bits;

first sense amplifiers coupled to one of the subarrays;

second sense amplifiers coupled to the other of the subarrays;

a selection circuit for selecting data from one of the first and second sense amplifiers in response to at least one bit of a non redundant-form address.

11. The memory defined by claim 10 wherein the one bit of the non redundant-form address is the least significant bit of the address.

12. The memory defined by claim 11 wherein the first and second sense amplifiers are coupled to common output lines.

13. The memory defined by claim 12 including a comparator coupled to receive a tag field from the selected one of the subarrays and non redundant-form address bits.

14. The memory defined by claim 10 including a comparator coupled to receive a tag field from the selected one of the subarrays and non redundant-form address bits.

15. A method for accessing a memory comprising:

selecting first and second data based on a redundant-form address; and

selecting between the first and second data based on at least one bit of a non redundant-form address.

16. The method defined by claim 15 wherein the one bit of the non redundant-form is the least significant bit of the address.

17. The method defined by claim 15 including the step of comparing part of the selected data with bits of non redundant-form address.

18. The memory defined by claim 17 wherein the one bit of the non redundant-form address is the least significant bit.

19. A method comprising the steps of:

decoding a redundant-form memory address;

selecting at least two word lines in a memory array based on the decoded redundant-form memory address;

selecting between the two lines based on at least one bit of a non redundant-form memory address;

comparing bits of the non redundant-form memory address with tag bits from the selected line.

20. The memory defined by claim 19 wherein the one bit of the non redundant-form memory address is the least significant bit of the address.

21. The method defined by claim 20 including the step of providing a hit/miss signal.