Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method

• US 6,707,822 B1
• Filed: 01/07/2000
• Issued: 03/16/2004
• Est. Priority Date: 01/07/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Soto, Walter G., Fadavi-Ardekani, Jalil, Xin, Weizhuang
• Primary Examiner(s): Ngo, Ricky
• Assistant Examiner(s): MEW, KEVIN D
• Application Number:
  US09/479,611
• Time in Patent Office: 1,530 Days
• Field of Search: 370/230, 370/235, 370/235.1, 370/395.1, 370/412, 370/428, 370/429, 370/395.5, 370/480, 370/503, 370/505, 370/511, 370/512, 370/513, 370/514, 370/516, 375/222
• US Class Current: 370/395.5
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI. IDIM holds DMT frames of data and may also be utilized in a ping-pang fashion. Memory is shared by multiple ADSL sessions and by the transmit and receive processes within an individual session.

Claims

1. A digital subscriber line (DSL) transceiver for a plurality of DSL sessions, said DSL transceiver comprising:

an asynchronous transfer mode (ATM) accelerator interfacing a plurality of ATM channels for each of said plurality of DSL sessions, said ATM accelerator operative to convert a first analog signal to a first bit stream, said ATM accelerator operative to convert a second bit stream, said ATM accelerator operative to convert a second bit stream to a second analog signal;

a frame memory bi-directionally coupled to said ATM accelerator, said frame memory operative to receive a bit stream and store said bit stream as a frame of data;

a framer/coder/interleaver (FCI) bi-directionally coupled to said frame memory, said FCI operative to perform a data operation on said frame of data;

an interleave/de-interleave memory (IDIM) bi-directionally coupled to said FCI, said IDIM operative to receive said frame of data and store said frame of data; and

a digital signal processing (DSP) core for performing a processing task, said DSP core bi-directionally coupled to said ATM accelerator, said frame memory and said IDIM,

wherein said DSP core includes a means to generate a periodic signal, wherein, responsive to said periodic signal, said transceiver performs a transmit process sequentially for a first subset of said plurality of DSL sessions and performs a receive process sequentially for a second subset of said plurality of DSL sessions.

2. The DSL transceiver of claim 1, wherein said periodic signal is generated at a frequency of 69/68×

4 KHz.

3. The transceiver of claim 1, wherein said data operation performed by said FCI is selected from the group consisting of framing, de-framing, error checking, scrambling, de-scrambling, encoding, de-coding, interleaving and de-interleaving.

4. The transceiver of claim 1, wherein said FCI further includes

a means for framing/de-framing said frame of data;

a means for error check generation and evaluation of said frame of data;

a means for scrambling/de-scrambling said frame of data;

a means for encoding/de-coding said frame of data; and

a means for interleaving/de-interleaving said frame of data.

5. The DSL transceiver of claim 1, wherein said FCI further includes:

a means for performing a transmit process sequentially for a first subset of said plurality of DSL sessions;

a means for generating a first signal indicating said transmit process for said first subset of said plurality of DSL sessions has been performed;

a means for performing a receive process sequentially for a second subset of said plurality of DSL sessions; and

a means for generating a second signal indicating said receive process for said second subset of DSL sessions has been performed.

6. The DSL transceiver of claim 1, wherein said FCI further includes

a means for generating and inserting a network timing reference;

a means providing interleave and fast path support; and

a means providing access to internal state and data of said FCI.

7. The DSL transceiver of claim 1, wherein said DSP core includes

a means to move said bit stream between said ATM accelerator and said frame memory;

a means to move said frame of data to said IDIM.

8. The DSL transceiver of claim 1, wherein said frame memory operates in a ping-pang fashion based on said periodic signal.

9. The DSL transceiver of claim 1, wherein said frame memory is a RAM of a size that supports at least two of said frames of data and operates in a ping-pang fashion.

10. The DSL transceiver of claim 1, wherein said IDIM further includes a fast path memory.

11. The DSL transceiver of claim 1, wherein said IDIM operates in a ping-pang fashion based on said periodic signal.

12. The DSL transceiver of claim 1, wherein said IDIM is a RAM of a size that supports at least four full depth G.lite sessions or approximately one full depth standard ADSL session.

13. The DSL transceiver of claim 1, wherein each of said plurality of DSL sessions supported by said DSL transceiver is XDSL selected from the group consisting of asymmetric DSL (ADSL), High bit-rate DSL (HDSL), and Very high bit rate DSL (VDSL).

14. The DSL transceiver of claim 1, wherein each of said plurality of DSL sessions supported by said DSL transceiver is modulated according to a modulation technology selected from the group consisting of Discrete Multitone, Carrierless Amplitude Modulation, and Multiple Virtual Line.

15. A method of buffering and scheduling for a multi-session digital subscriber line (DSL) transceiver, said method comprising the steps of generating a periodic signal, said periodic signal having a rising edge and a declining edge;

responsive to said rising edge of said periodic signal, sequentially performing a transmit process for each of a first plurality of DSL sessions, said transmit process utilizing a first memory;

generating a first signal indicative of a completion of said transmit process for said first plurality of DSL sessions;

responsive to said first signal, sequentially performing a receive process for a second plurality of DSL sessions, said receive process utilizing a second memory; and

generating a second signal indicative of a completion of said receive process for said second plurality of DSL sessions.

16. The method of buffering and scheduling of claim 15 wherein said first memory and said second memory are the same.

17. The method of buffering and scheduling of claim 16 wherein said first memory and said second memory are operated in a ping-pang fashion based on a state of said periodic signal.

18. A digital subscriber line (DSL) transceiver for transmitting and receiving data for a plurality of DSL sessions, said DSL transceiver composing:

an asynchronous transfer mode (ATM) accelerator interfacing a plurality of asynchronous transfer mode channels for each of a plurality of DSL sessions, said ATM accelerator including a means to perform a first transmit process and a means to perform a first receive process on frame data;

a frame buffer for holding said frame data;

a framer/coder/interleaver (FCI) interfacing said ATM accelerator through said frame buffer, said FCI including a means to perform a second transmit process and a means to perform a second receive process on said frame data;

an interleave/de-interleave memory (IDIM); and

a digital signal processing (DSP) core interfacing said FCI through said IDIM, said DSP core including a means to perform a third transmit process and a means to perform a third receive process on said frame data;

wherein said first transmit process, said second transmit process and said third transmit process are characterized as transmit processing, and said first receive process, said second receive process and said third receive process are characterized as receive processing; and

wherein said DSP core includes a means to generate a periodic signal, said periodic signal operative to initiate a performance of transmit processing sequentially for a first subset of said plurality of DSL sessions and a performance of a receive processing sequentially for a second subset of said plurality of DSL sessions.

19. The DSL transceiver of claim 18, wherein said periodic signal is generated at a frequency of 69/68×

4

Khz.

20. The DSL transceiver of claim 18, wherein said first transmit process converts a first bit stream to a first analog signal and said first receive process converts a second analog signal to a second bit stream.

21. The DSL transceiver of claim 18, wherein said second transmit process is selected from the group consisting of framing, error check generation, scrambling, encoding, and interleaving.

22. The DSL transceiver of claim 18, wherein said second receive process is selected from the group consisting of de-framing, error check evaluation, de-scrambling, de-coding and de-interleaving.

23. The DSL transceiver of claim 18, wherein said third transmit process and said third receive process comprises moving said frame data.

24. A DSL transceiver of claim 18, wherein said frame buffer is a RAM buffer operated in a ping-pang fashion based on said periodic signal.

25. A DSL transceiver of claim 18, wherein said IDIM is a RAM buffer operated in a ping-pang fashion based on said periodic signal.

26. A DSL transceiver of claim 18, wherein said IDIM is a RAM buffer sized to support at least four full depth G.lite sessions or approximately one full depth standard ADSL session.