Multiple-output counters for analog-to-digital and digital-to-analog conversion

• US 6,707,874 B2
• Filed: 04/15/2002
• Issued: 03/16/2004
• Est. Priority Date: 04/15/2002
• Status: Expired due to Fees

• Current Assignee: Charles Douglas Murphy
• Original Assignee: Charles Douglas Murphy
• Inventors: Murphy, Charles Douglas
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US10/122,654
• Publication Number:
  US 20030194047A1
• Time in Patent Office: 701 Days
• Field of Search: 377/33, 377/34, 377/35, 377/36, 377/56
• US Class Current: 377/33
• CPC Class Codes: H03K 21/12 with parallel read-out

Abstract

A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Claims

1. A machine used for digital counting in data conversion, comprising:

a. a first output count

i. said first output count being provided in a first finite-precision numeric format having more than one bit of precision

ii. said first output count being a first data conversion digital reference signal

b. a second output count which is not identical to said first output count

i. said second output count being provided in a second finite-precision numeric format having more than one bit of precision

ii. said second output count being a second data conversion digital reference signal

c. shared means for generating said first output count and said second output count

whereby said machine for digital counting can provide two different output counts generated using shared components rather than entirely separate compones, and whereby said machine for digital counting can provide said two different output counts as data conversion digital reference signals for analog-to-digital data conversion, for digital-to-analog data conversion, or for both analog-to-digital and digital-to-analog data conversion.

2. The machine of claim 1 in which:

a. said first output count changes in a first direction from the direction set consisting of increasing or decreasing

b. said second output count changes in a second direction from said direction set

c. said second direction is not the same as said first direction

whereby said first output count increases and said second output count decreases, or whereby said first output count decreases and said second output count increases.

3. The machine of claim 1 in which:

a. said first output count changes in a first direction from the direction set consisting of increasing or decreasing

b. said second output count changes in a second direction from said direction set

c. said second direction is the same as said first direction

whereby said first output count and said second output count both increase, or whereby said first output count and said second output count both decrease.

4. The machine of claim 1 further including means for switching between providing said first output count and providing said second output count, whereby said machine provides two different counts, but does not do so simultaneously.

5. The machine of claim 1 further including means for providing said first output count and said second output count simultaneously.

6. The machine of claim 1 in which said first finite-precision numeric format is the same format as said second finite-precision numeric format.

7. The machine of claim 6 in which said first finite-precision numeric format is a first format from a format set consisting of two'"'"'s complement formats and offset binary formats.

8. The machine of claim 7 further including means for complementing the sign bit of a representation of a value of said first output count to obtain the sign bit of the representation of a corresponding value of said second output count.

9. The machine of claim 7 further including means for complementing a multiplicity of non-sign bits of a representation of a value of said first output count to obtain a multiplicity of non-sign bits of the representation of a corresponding value of said second output count.

10. The machine of claim 6 in which said first finite-precision numeric format is a sign magnitude format.

11. The machine of claim 10 further including means for complementing the sign bit of a representation of a value of said first output count to obtain the sign bit for the representation of a corresponding value of said second output count.

12. The machine of claim 11 further including means for complementing a multiplicity of magnitude bits of a representation of a value of said first count to obtain a multiplicity of magnitude bits for the representation of the corresponding value of said second output count.

13. The machine of claim 1 in which said first finite-precision numeric format is not the same finite-precision numeric format as said second finite-precision numeric format, whereby said machine for digital counting can provide output counts in different finite-precision numeric formats.

14. The machine of claim 13 in which:

a. said first finite-precision numeric format is a member of a first format set from the set of format sets consisting of the set of offset binary formats and the set of two'"'"'s complement formats

b. said second finite-precision numeric format is a member of a second format set from said set of format sets

c. said second format set is not the same set as said first format set

whereby said machine for digital counting can provide one output count in an offset binary format and one count in a two'"'"'s complement format.

15. The machine of claim 14 further including means for complementing the sign bit of a representation of a value of said first output count to obtain the sign bit of the representation of a corresponding value of said second output count.

16. The machine of claim 13 in which:

a. said first finite-precision numeric format is a member of a first format set from the set of format sets consisting of the set of sign magnitude formats and the set of two'"'"'s complement and offset binary formats

b. said second finite-precision numeric format is a member of a second format set from said set of format sets

c. said second format set is not the same set as said first format set

whereby said machine for digital counting can provide one output count in an sign magnitude format and one count in a two'"'"'s complement format or in an offset binary format.

17. The machine of claim 16 in which said first finite-precision numeric format is a member of a two-member format set consisting of a sign-magnitude format and an offset binary format and in which said second finite-precision numeric format is the other member of said two-member set, further including:

a. means for determining the state of a sign bit in a first representation of a first value of said first output count

b. means for complementing said sign bit in said first representation

c. means for complementing non-sign bits in said first representation elements depending on said state

d. means for adding, depending on said state, a bit value of one to a least-significant bit which is a member of the set of complemented non-sign bits, with overflow at the most significant non-sign bit discarded rather than carried over to said sign bit

whereby a representation of said second output count is produced from a representation of said first output count, and whereby a number representation in a sign-magnitude format can be converted to a corresponding representation in an offset binary format, or whereby a number representation in an offset binary format can be converted to a corresponding representation in a sign-magnitude format.

18. The machine of claim 16 in which said first finite-precision numeric format is a member of a two-member format set consisting of a sign-magnitude format and a two'"'"'s complement format and in which said second finite-precision numeric format is the other member of said two-member set, further including:

a. means for determining the state of a sign bit in a first representation of a first value of said first output count

b. means for complementing non-sign bits in said first representation depending on said state

c. means for adding, depending on said state, a bit value of one to a least-significant bit which is a member of the set of complemented non-sign bits, with overflow at the most significant non-sign bit discarded rather than carried over to said sign bit

whereby a representation of said second output count is produced from a representation of said first output count, and whereby a number representation in a sign-magnitude format can be converted to a corresponding representation in a two'"'"'s complement format, or whereby a number representation in a two'"'"'s complement format can be converted to a corresponding representation in a sign-magnitude format.

19. The machine of claim 1 further including an inverter.

20. The machine of claim 1 further including means for initializing said first output count to a constant value, whereby said first output count can be reset to a single desired initial value.

21. The machine of claim 1 further including means for initializing said first output count to a variable value, whereby different desired initial values can be used for said first output count.

22. The machine of claim 1 further including:

a. means for storing representations of two or more count values of said first output count

b. means for selecting one or more of the stored representations to provide as output

whereby results of counting are not discarded immediately, so that representations of count values plus or minus correction terms are available without additional arithmetic operations beyond those implemented for the counting itself.

23. The machine of claim 1 further including means for using said first output count, said second output count, or both said first output count and said second output count for a first digital-to-analog conversion.

24. The machine of claim 23 further including:

a. a multiplicity of analog reference signals generated in parallel

b. a multiplicity of output counts corresponding to said multiplicity of analog reference signals, said multiplicity of output counts comprising said first output count, said second output count, or both said first output count and said second output count

c. means for comparing a first digital input number to said multiplicity of output counts and for producing a first digital number equality signal

d. means for acquiring a first analog output signal on receiving said first digital number equality signal, said first analog output signal having a level equal to the analog reference signal to which a member of said multiplicity of output counts corresponds, said member being indicated by said first digital number equality signal

whereby said first output count and said second output count may correspond to differing analog reference signals in a digital-to-analog converter in which parallel digital comparisons and analog reference signals enable faster conversion that would be possible with a single analog reference signal such as a single switched analog reference source or a single analog ramp.

25. The machine of claim 23 further including:

a. an analog triangle wave signal

b. a digital comparator

c. means for providing said first output count and a first digital number as inputs to said digital comparator during a first rising portion of said triangle wave

d. means for using the output of said digital comparator during said first rising portion of said triangle wave to trigger recording of a first analog output value

e. means for providing said second output count and a second digital number as inputs to said digital comparator during a first falling portion of said triangle wave

f. means for using the output of said digital comparator during said first falling portion of said triangle wave to trigger recording of a second analog output value

whereby said first digital number is converted to said first analog output value and whereby said second digital number is converted to said second analog output value, and whereby generation of said first output count and said second output count do not require separate counters.

26. The machine of claim 23 further including means for using said first output count, said second output count, or both said first output count and said second output count for a second digital-to-analog conversion which occurs in parallel with said first digital-to-analog conversion.

27. The machine of claim 26 further including:

a. a first analog triangle wave signal

b. a second analog triangle wave signal

c. a first digital comparator

d. a second digital comparator

e. means for providing said first output count and a first digital number as inputs to said first digital comparator during a first rising portion of said first triangle wave

f. means for using the output of said first digital comparator during said first rising portion of said first triangle wave to trigger recording of a first analog output value

g. means for providing said second output count and a second digital number as inputs to said second digital comparator during a first falling portion of said second triangle wave

h. means for using the output of said second digital comparator during said first falling portion of said second triangle wave to trigger recording of a second analog output value

whereby said first digital number can be converted to said first analog output value and whereby said second digital number can be converted to said second analog output value simultaneously, with generation of said first output count and said second output count not requiring separate counters.

28. The machine of claim 23 in which said first finite-precision numeric format is not the same as said second finite-precision numeric format, further including:

a. an analog reference signal

b. a first digital number

c. a first digital comparator having as a first input said first digital number

d. means for selecting said first output count or said second output count to provide as a second input to said first digital comparator

e. means for using the output of said digital comparator to trigger recording of a first analog output value

whereby digital-to-analog conversion of said first digital number to said first analog output value can accommodate said first digital input number being in said first finite-precision numeric format or in said second finite-precision numeric format, for instance, said first digital input number being in a two'"'"'s complement format or in an offset binary format.

29. The machine of claim 23 further including means for using said first output count, said second output count, or both said first output count and said second output count for circuit error compensation in a first digital-to-analog conversion.

30. The machine of claim 1 further including means for using said first output count, said second output count, or both said first output count and said second output count for a first analog-to-digital conversion.

31. The machine of claim 30 further including means for using said first output count, said second output count, or both said first output count and said second output count for circuit error compensation in said first analog-to-digital conversion.

32. The machine of claim 31 further including:

a. means for recording a first count value representative in a first manner of an analog input signal level and also of a circuit error signal

b. means for recording a second count value representative in a second manner of said analog input signal level and of said circuit error signal

c. means for operating on said first count value and said second count value using an arithmetic operation from the set consisting of addition and subtraction to produce a third count value

whereby said third count value can be representative of said circuit error signal or representative of said analog input signal level, depending on the circuit structure and the arithmetic operation used, whereby circuit error signals such as the dielectric effect in a capacitor or the comparator offset signal of a comparator can be corrected.

33. The machine of claim 31 further including:

a. means for recording a first count value representative in a first manner of an analog input signal level and also of a circuit error signal

b. means for determining a circuit error signal

c. means operating on said first count value to produce a second count value using an arithmetic operation from the set consisting of addition and subtraction

whereby said second count value is representative of said analog input signal level, whereby circuit error signals such as the dielectric effect in a capacitor or the comparator offset signal of a comparator can be corrected.

34. The machine of claim 31 further including means for using said first output count, said second output count, or both said first output count and said second output count for circuit error compensation in a second analog-to-digital conversion, whereby circuit error signals such as the dielectric effects in a multiplicity of capacitors and the comparator offset signals of a multiplicity of comparators can be corrected using a single multiple-output counter.