High security flash memory and method
First Claim
1. An integrated circuit comprising:
- a sensor that reads a fingerprint and provides data corresponding to the fingerprint; and
a computation engine coupled to the sensor that compares the data to stored data, the computation engine enabling a smart card coupled to the computation engine when the data and the stored data match, the computation engine including, an array of flash memory cells arranged in pairs of rows, flash memory cells in any one row having sources coupled to a common row line;
a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows; and
a buffer circuit formed in each neuron that sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron.
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Abstract
An integrated circuit includes a sensor that reads a fingerprint and provides data corresponding to the fingerprint to a computation engine coupled to the sensor. The computation engine compares the data to stored data and enables a smart card coupled to the computation engine when the data and the stored data match. The computation engine may include an array of flash memory cells arranged in pairs of rows, where flash memory cells in any one row have sources coupled to a common row line and a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows. The neurons are coupled to the flash memory cells through a buffer circuit sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron.
15 Citations
13 Claims
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1. An integrated circuit comprising:
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a sensor that reads a fingerprint and provides data corresponding to the fingerprint; and
a computation engine coupled to the sensor that compares the data to stored data, the computation engine enabling a smart card coupled to the computation engine when the data and the stored data match, the computation engine including, an array of flash memory cells arranged in pairs of rows, flash memory cells in any one row having sources coupled to a common row line;
a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows; and
a buffer circuit formed in each neuron that sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron. - View Dependent Claims (2, 3)
a controller that determines how many times the data and the stored data do not match; and
circuitry that disables the computation engine when the number of times that the data and the stored data do not match exceeds a predetermined threshold.
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3. The circuit of claim 1, wherein the computation engine disables the smart card when the data and the stored data do not match.
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4. An instrument comprising:
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a sensor that reads a fingerprint and provides input data corresponding to the fingerprint;
a computation engine coupled to the sensor that compares the input data to stored data, the computation engine including;
an array of flash memory cells arranged in pairs of rows, flash memory cells in any one row having sources coupled to a common row line;
a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows; and
a buffer circuit formed in each neuron that sets a drain source voltage to cause the flash memory cells in the row pair coupled to the neuron to operate; and
a smart card coupled to the computation engine that is enabled when the input data and the stored data match. - View Dependent Claims (5, 6)
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7. The integrated circuit comprising:
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a sensor that reads a fingerprint and provides data corresponding to the fingerprint; and
a computation engine coupled to the sensor that compares the data to stored data, the computation engine enabling a smart card coupled to the computation engine when the data and the stored data match, the computation engine including, an array of flash memory cells arranged in pairs of rows, flash memory cells in any one row having sources coupled to a common row line;
a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows; and
a buffer circuit formed in each neuron that sets a drain-source voltage to cause the flash memory cells in the row pair coupled to the neuron to operate in the triode region.
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8. An integrated circuit comprising;
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a sensor that reads a fingerprint and provides input data corresponding to the fingerprint; and
a matrix of row and column conductors;
a capacitor plate located at each intersection of the row and column conductors, the capacitor being coupled to the row conductor through a first transistor and to the column conductor through a second transistor; and
sensing circuitry coupled to the matrix; and
a computation engine coupled to the sensor that compares the data to stored data, the computation engine enabling a smart card coupled to the computation engine when the input data and the stored data match.
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9. A fingerprint sensor circuit comprising:
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a matrix of row conductors and column conductors;
a fingerprint sensing array having a sensing cell located at each intersection of the row and column conductors, the sensor cell being coupled to a row conductor and to a column conductor, the row and column conductors being selectively enabled in their electrical connection to a sensing cell in order to individually address each sensing cell;
sensing circuitry coupled to the matrix; and
a computation engine coupled to the sensing circuitry that compares sensed data to stored data and outputting an enable signal when the sensed data and the stored data match each other. - View Dependent Claims (10)
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11. An integrated circuit comprising:
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a sensor that reads a fingerprint and provides input data corresponding to the fingerprint;
an array of flash memory cells arranged in pairs of rows, the flash memory cells in any one row having sources coupled to a common line;
a plurality of conductance mode circuits each having an input coupled to a respective row of the flash memory cells;
a buffer circuit formed in each conductance mode circuit that sets a drain-source voltage of the flash memory cells in the respective row coupled to such conductance mode circuit; and
a computation engine that compares input data to stored data. - View Dependent Claims (13)
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12. A fingerprint sensor circuit comprising:
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a matrix of row conductors and column conductors;
a sensing cell for a fingerprint located at each intersection of the row and column conductors, each sensor cell being coupled to the row conductor through a first transistor and to the column conductor through a second transistor;
sensing circuitry coupled to the matrix of row and column conductors; and
a computation engine coupled to the sensing circuitry that compares input data to stored data, the computation engine outputting an enable signal when the input data matches the stored data.
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Specification