Parallel access virtual channel memory system
First Claim
1. A method of accessing a memory array with a plurality of memory masters, the method comprising:
- coupling a virtual access system to the memory array, wherein the virtual access system comprises a plurality of virtual access channels connected in parallel to the memory array, each virtual access channel providing a set of memory access resources for accessing the memory array;
assigning each of the memory masters to access one or more of the virtual access channels;
providing address signals from the memory masters to the virtual access system; and
accessing a selected one of the virtual access channels in response to the address signals.
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Accused Products
Abstract
A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.
116 Citations
14 Claims
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1. A method of accessing a memory array with a plurality of memory masters, the method comprising:
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coupling a virtual access system to the memory array, wherein the virtual access system comprises a plurality of virtual access channels connected in parallel to the memory array, each virtual access channel providing a set of memory access resources for accessing the memory array;
assigning each of the memory masters to access one or more of the virtual access channels;
providing address signals from the memory masters to the virtual access system; and
accessing a selected one of the virtual access channels in response to the address signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
storing a cache entry and a corresponding cache address entry in the selected one of the virtual access channels;
comparing the address signals with the cache address entry; and
accessing the cache entry corresponding if the current access address matches the cache address entry.
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3. The method of claim 2, further comprising:
accessing the memory array through a bus bypass circuit and updating the selected one of the virtual access channels to reflect this accessing if the address signals do not match the cache address entry.
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4. The method of claim 1, further comprising:
simultaneously activating two of the virtual access channels.
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5. The method of claim 1, further comprising:
chaining a plurality of the virtual access channels.
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6. The method of claim 1, further comprising:
independently assigning a burst length to each of the virtual access channels.
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7. The method of claim 1, further comprising:
independently assigning a precharge mode to each of the virtual access channels.
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8. The method of claim 1, further comprising:
prefetching data from the memory array to a selected one of the virtual access channels in response to a prefetch command issued by one of the memory masters.
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9. The method of claim 8, further comprising:
transferring data between one of the memory masters and one of the virtual access channels concurrently with the prefetching.
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10. The method of claim 8, further comprising:
restoring data from a selected one of the virtual access channels to the memory array in response to a restore command issued by one of the memory masters, wherein the restoring is performed concurrently with the prefetching.
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11. The method of claim 1, wherein the memory array comprises a plurality of memory banks, the method further comprising:
concurrently prefetching data from a plurality of the multiple banks to a corresponding plurality of the virtual access channels in response to a plurality of prefetch commands issued by the memory masters.
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12. The method of claim 11, further comprising:
restoring data from a selected one of the virtual access channels to the memory array in response to a restore command issued by one of the memory masters.
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13. The method of claim 12, further comprising:
transferring data between one of the memory masters and one of the virtual access channels concurrently with the restoring.
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14. The method of claim 1, wherein the memory array comprises a plurality of memory banks, the method further comprising:
concurrently restoring data from a plurality of the virtual access channels to a corresponding plurality of the memory banks in response to a plurality of restore commands issued by the memory masters.
Specification