Buffering system bus for external-memory access

• US 6,708,257 B2
• Filed: 07/12/1999
• Issued: 03/16/2004
• Est. Priority Date: 07/12/1999
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Bao, Liewei
• Primary Examiner(s): Bragdon, Reginald G.
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/351,053
• Publication Number:
  US 20010052060A1
• Time in Patent Office: 1,709 Days
• Field of Search: 711/119, 711/154, 711/102-105, 711/138, 711/159, 711/165, 710/112, 710/36, 710/38-39, 710/52, 710/57, 710/107, 710/310, 710/313
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A computer system includes a processor, a cache, a system bus, a memory-control subsystem, an external memory bus, RAM memory, and flash memory. All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller, a flash-memory controller, and a memory interface between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer. During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers. While the processor write buffer frees the processor for other tasks while a write operation is being completed, the system-bus write buffer frees the system bus for other tasks while a write operation is being completed. The system-bus buffer thus allows other operations to utilize the system bus during an external-memory access.

Claims

1. A computer system, comprising:

a processor;

a first buffer coupled to the processor by a first bus;

a second buffer coupled to the first buffer by a second bus;

a local memory coupled to the second bus;

a first memory controller coupled to the processor by the second bus, further coupled to the second buffer, and further coupled to a memory interface; and

a second memory controller coupled to the processor by the second bus, further coupled to the second buffer, and further coupled to the memory interface;

wherein the second buffer for storing data-transfer requests, the second buffer is coupled to the memory interface, and the memory interface is adapted to transmit data to, and receive data from a third bus;

a first memory and a second memory, each coupled to the third bus, wherein the first memory is connected to the first memory controller, and the second memory is connected to the second memory controller; and

a read bypass path, the read bypass path connected to the memory interface, and adapted to transfer data from the memory interface to the second bus without having the data pass through the second buffer.

2. The computer system of claim 1, wherein the first memory is a RAM, and the first memory controller is adapted to provide control signals to the RAM.

3. The computer system of claim 2, wherein the first memory controller is adapted to generate one or more signals to prevent the second memory controller from accessing the third bus.

4. The computer system of claim 3, wherein the second memory controller is adapted to generate one or more signals to prevent the first memory controller from accessing the third bus.

5. The computer system of claim 4, wherein the first and second memory controllers are further adapted to generate signals that prevent access to a system bus by either the processor or the local memory until a transfer between the second bus and the second buffer is complete.

6. The computer system of claim 1, wherein the second memory is a flash memory, and the second memory controller is adapted to provide control signals to the flash memory.

7. A method of operating a computer system, comprising:

generating a plurality of write-requests from a processor;

responsive to the write-requests, transferring data and control information corresponding to those write-requests over a system bus to a system bus buffer;

generating a signal indicating that the system bus buffer is full;

generating a read-request from the processor;

responsive to the read-request, bypassing the system bus buffer and transferring data from an external memory bus to the system bus.

8. The method of claim 7, further comprising:

generating control signals to operate a first memory and transferring data from the system bus buffer to the first memory via an external memory bus.

9. The method of claim 8, further comprising:

generating control signals to operate a second memory and transferring data from the system bus buffer to the second memory via the external memory bus.

10. The method of claim 9, wherein the first memory is a RAM and the second memory is a flash memory.

11. The method of claim 9, further comprising transferring data between the processor and a local memory over the system bus concurrently with data being transferred between the system bus buffer and one of the first or second memories over the external memory bus.