Method for inspecting a pattern defect process

• US 6,709,879 B2
• Filed: 01/02/2002
• Issued: 03/23/2004
• Est. Priority Date: 01/02/2002
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yeh, Chia-Fu
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US10/038,691
• Publication Number:
  US 20030124749A1
• Time in Patent Office: 811 Days
• Field of Search: 438/16, 438/585, 430/315
• US Class Current: 438/16
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0002 Inspection of images, e.g. flaw detection
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311

Abstract

A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device profile. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.

Claims

1. A method for inspecting a pattern defect process, said method comprising:

providing a substrate;

forming a device on said substrate, wherein said device comprises a defect portion;

forming a layer on said device and said substrate, wherein said layer has an etch selectivity different from the etch selectivity of said device;

removing said layer partially to stop on said device and to form a reverse mask;

etching said device on said substrate by using said reverse mask as a mask; and

removing said reverse mask.

2. The method for inspecting a pattern defect process according to claim 1, wherein said device comprises a gate.

3. The method for inspecting a pattern defect process according to claim 2, wherein thickness of said gate is between about 3000 and 8000 angstroms.

4. The method for inspecting a pattern defect process according to claim 2, wherein said device material is polysilicon.

5. The method for inspecting a pattern defect process according to claim 1, wherein said layer is formed by using spin coating method.

6. The method for inspecting a pattern defect process according to claim 1, wherein said layer is selected from the group consisting of photoresist and silicon nitride.

7. A method for raising a signal-to-noise ratio for defect inspection on a substrate, said method comprising:

providing a device profile on said substrate, said device profile comprising a defect portion;

forming a layer on said device profile and said substrate, wherein the etch selectivity of said layer is different from the etch selectivity of said device profile;

planarizing said layer to form a reverse mask of said device profile;

removing said device profile by using said reverse mask as a mask to remain said defect portion on said substrate; and

removing said reverse mask so as to remain said defect portion on said substrate, whereby said defect portion is used to raise said signal-to-noise for defect inspection.

8. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 7, wherein said providing the device profile comprises:

forming a polysilicon layer on said substrate; and

removing a portion of the polysilicon layer to form said device profile.

9. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 8, wherein said device profile further comprises forming a gate device.

10. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 7, wherein said planarizing step comprises etching said layer back.

11. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 7, wherein said layer comprises coating a spinning-on layer.

12. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 11, wherein said spinning-on layer comprises a photoresist layer.

13. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 7, wherein said layer comprises a silicon nitride layer.

14. A method for raising a signal-to-noise ratio for defect inspection on a substrate, said method comprising:

providing a gate device on said substrate, said gate device comprising a defect portion;

forming a layer on said gate device and said substrate, wherein the etch selectivity of said layer is different from the etch selectivity of said gate device, wherein said layer is selected from the group consisting of photoresist and silicon nitride;

etching said layer to form a reverse mask of said gate device;

removing said gate device by using said reverse mask as a mask to remain said defect portion on said substrate; and

removing said reverse mask so as to remain said defect portion on said substrate, whereby said defect portion is used to raise said signal-to-noise for defect inspection.

15. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 14, wherein said providing the gate device comprises:

forming a polysilicon layer on said substrate; and

removing a portion of the polysilicon layer to form said gate device.

16. The method for raising a signal-to-noise ratio for defect inspection on a substrate according to claim 14, wherein said layer comprises coating a spinning-on layer.