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Split-gate flash memory cell and manufacturing method thereof

  • US 6,709,925 B1
  • Filed: 12/12/2002
  • Issued: 03/23/2004
  • Est. Priority Date: 09/19/2002
  • Status: Expired due to Term
First Claim
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1. A method for manufacturing a split-gate flash memory cell, the method comprising the steps of:

  • (a) providing a substrate;

    (b) forming a tunnel oxide layer over the substrate;

    (c) forming a tip type peak floating gate layer of conducting material over a portion of said tunnel oxide layer, wherein said tip type peak floating gate layer includes a tip and an angle of said tip is substantially less than 90 degrees;

    (d) forming an inter-gate insulating layer over said tip type peak floating gate layer wherein said inter-gate insulating layer generally follows a topology of said tip type peak floating gate layer;

    (e) forming a control gate layer of conducting material over said inter-gate insulating layer, wherein said control gate layer generally follows a topology of said inter-gate insulating layer and said tip type peak floating gate layer;

    (f) patterning a gate electrode and etching down said control gate layer, said inter-gate insulating layer, said tip type peak floating gate layer, and said tunnel oxide layer;

    (g) defining a source and a drain adjoining the tunnel oxide region by using a self-align technique.

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