Split-gate flash memory cell and manufacturing method thereof

• US 6,709,925 B1
• Filed: 12/12/2002
• Issued: 03/23/2004
• Est. Priority Date: 09/19/2002
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: ANAM Semiconductor Incorporated (DB HiTek Co., Ltd.)
• Inventors: Choi, Tae Ho, Kim, Jae Yeong
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/316,904
• Publication Number:
  US 20040058494A1
• Time in Patent Office: 467 Days
• Field of Search: 438/201, 438/211, 438/257, 438/264, 438/266, 438/267, 438/593, 438/594
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate

Abstract

A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Claims

1. A method for manufacturing a split-gate flash memory cell, the method comprising the steps of:

(a) providing a substrate;

(b) forming a tunnel oxide layer over the substrate;

(c) forming a tip type peak floating gate layer of conducting material over a portion of said tunnel oxide layer, wherein said tip type peak floating gate layer includes a tip and an angle of said tip is substantially less than 90 degrees;

(d) forming an inter-gate insulating layer over said tip type peak floating gate layer wherein said inter-gate insulating layer generally follows a topology of said tip type peak floating gate layer;

(e) forming a control gate layer of conducting material over said inter-gate insulating layer, wherein said control gate layer generally follows a topology of said inter-gate insulating layer and said tip type peak floating gate layer;

(f) patterning a gate electrode and etching down said control gate layer, said inter-gate insulating layer, said tip type peak floating gate layer, and said tunnel oxide layer;

(g) defining a source and a drain adjoining the tunnel oxide region by using a self-align technique.

2. The method of claim 1, wherein the step (c) includes the steps of:

(c1) depositing said floating gate layer of conducting material over the tunnel oxide layer;

(c2) forming a mask layer of insulating material over said floating gate layer;

(c3) using said mask layer to etch down a predetermined portion of said floating gate layer steeply to said tunnel oxide layer so that a sloping-patterned floating gate layer with a sloping sidewall is formed;

(c4) forming a spacer of insulating material to cover at least the sloping sidewall of the sloping-patterned floating gate layer therewith and removing said mask layer; and

(c5) using the spacer to etch down said sloping-patterned floating gate layer steeply with a predetermined depth so that said tip type peak floating gate layer is formed and removing the spacer.

3. The method of claim 1, wherein said tip is located around the drain.

4. The method of claim 2, wherein said mask layer has an etching selectivity different from that of said spacer.