Thicker oxide formation at the trench bottom by selective oxide deposition

• US 6,709,930 B2
• Filed: 06/21/2002
• Issued: 03/23/2004
• Est. Priority Date: 06/21/2002
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chan, Ben, Chang, David, Pattanayak, Deva, Terrill, Kyle, Lui, Kam Hong, Wong, Ronald, Xu, Robert Q., Yue, Christiana, Chen, Kuo-in, Giles, Frederick P., Darwish, Mohamed N.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/176,570
• Publication Number:
  US 20030235958A1
• Time in Patent Office: 641 Days
• Field of Search: 438/212, 438/268, 438/270, 438/272, 438/431, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

Claims

1. A method of fabricating a trench MOSFET, the method comprising:

providing a semiconductor substrate;

forming a trench in the substrate, the trench comprising a side wall and a bottom;

forming a thin insulating layer overlying the side wall and the bottom of the trench;

forming a barrier layer overlying the thin insulating layer on at least a portion of the side wall;

etching the thin insulating layer to form an exposed portion of the semiconductor substrate in the bottom of the trench; and

depositing a thick insulating layer overlying the bottom of the trench;

wherein the barrier layer is selected such that the thick insulating layer deposits on the semiconductor substrate at a faster rate than the thick insulating layer deposits on the barrier layer.

2. The method of claim 1 wherein forming a barrier layer comprises forming a silicon nitride layer by chemical vapor deposition.

3. The method of claim 1 wherein forming a barrier layer comprises thermally growing a silicon dioxide layer.

4. The method of claim 1 wherein forming a barrier layer comprises depositing a layer of silicon dioxide by plasma-enhanced chemical vapor deposition using TEOS as a precursor.

5. The method of claim 1 wherein forming a barrier layer comprises:

depositing a conformal layer; and

etching the conformal layer to form an opening in the conformal layer;

wherein the opening overlies a portion of the bottom of the trench.

6. The method of claim 1 wherein forming a barrier layer comprises:

depositing a conformal layer; and

etching the conformal layer to form an opening in the conformal layer;

wherein the opening overlies the bottom of the trench and a portion of the side wall adjacent to the bottom of the trench.

7. The method of claim 1 wherein the thick insulating layer is silicon dioxide.

8. The method of claim 1 wherein depositing a thick insulating layer comprises depositing a thick insulating layer by sub atmospheric chemical vapor deposition.

9. The method of claim 8 wherein depositing a thick insulating layer by sub atmospheric chemical vapor deposition further comprises introducing ozone and TEOS into a reactor.

10. The method of claim 1 further comprising forming a high conductivity region in the substrate adjacent to a portion of the bottom of the trench.

11. The method of claim 1 further comprising:

forming a body region in the substrate, the body region being located adjacent to the side wall; and

forming a source region in the body region, the source region being located adjacent to the side wall and to a top surface of the substrate.

12. The method of claim 1 further comprising depositing doped polysilicon in the trench.

13. The method of claim 1 wherein forming a thin insulating layer overlying the side wall and the bottom of the trench occurs prior to depositing a thick insulating layer overlying the bottom of the trench.