Narrow high performance MOSFET device design

• US 6,709,936 B1
• Filed: 06/10/2003
• Issued: 03/23/2004
• Est. Priority Date: 11/13/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Naem, Abdalla
• Primary Examiner(s): Everhart, Caridad
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US10/458,450
• Time in Patent Office: 287 Days
• Field of Search: 257/346, 257/365, 257/387, 257/388, 257/401, 257/412, 257/413, 257/286, 438/149-151, 438/163, 438/164, 438/194, 438/217, 438/225, 438/289, 438/294-297, 438/353, 438/400-430, 438/282, 438/156
• US Class Current: 438/297
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out

Abstract

The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. Four substrate diffusion regions, each having a second conductivity type opposite the first conductivity type, are formed in the substrate diffusion region in a respective comer of the substrate region. The four diffusion regions are spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions. A common conductive gate electrode is formed to have four fingers, each one of the fingers extending over a corresponding substrate channel region. The fingers of the common conductive gate electrode are spaced-apart from the underlying substrate channel regions by dielectric material formed therebetween.

Claims

1. A method of forming a high performance MOSFET transistor structure, the method comprising:

forming a region of dielectric material in a center region of a rectangular-shaped semiconductor substrate region having a first conductivity type;

forming a layer of gate dielectric material over the semiconductor substrate region;

forming a layer of conductive material over the layer of gate dielectric material;

patterning the layer of conductive material to define a common conductive gate electrode having first, second, third and fourth fingers, each finger extending over a corresponding channel region of the semiconductor substrate region and separated from the semiconductor substrate region by intervening gate dielectric material; and

forming first, second, third and fourth diffusion regions having a second conductivity type, each diffusion region being formed at a respective corner of the semiconductor substrate region such that a channel region is defined between each adjacent pair of diffusion regions.

2. A method of forming a high performance MOSFET transistor structure, the method comprising:

forming shallow trench isolation silicon oxide in a silicon substrate to define an isolated rectangular silicon device region in the silicon substrate and simultaneously forming a region of silicon oxide in the silicon device region at a center region of the silicon device region;

forming a layer of gate silicon oxide over the silicon device region;

forming a layer of polysilicon over the layer of gate silicon oxide;

patterning the layer of polysilicon to define a common polysilicon gate electrode of the MOSFET transistor structure, the gate electrode having first, second, third and fourth fingers, each finger extending outwardly from a common gate electrode central region formed over the central silicon oxide region, each finger extending over a corresponding channel region of the MOSFET transistor structure and separated therefrom by intervening gate silicon oxide;

forming first, second, third and fourth dopant diffision regions having a second conductivity type opposite the first conductivity type, each dopant diffusion region being formed at a respective corner of the silicon device region such that a channel region is defined between each adjacent pair of dopant diffusion region;

forming a first electrical contact to the first and third dopant diffusion regions to define source regions of the MOSFET transistor structure; and

forming a second electrical contact to the second and fourth dopant diffusion regions to define drain regions of the MOSFET transistor structure.