Semiconductor wafer edge marking

• US 6,710,364 B2
• Filed: 06/20/2002
• Issued: 03/23/2004
• Est. Priority Date: 09/24/1999
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Melcher, Keith W., Williston, John, Guldi, Richard L.
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US10/178,627
• Publication Number:
  US 20020153620A1
• Time in Patent Office: 642 Days
• Field of Search: 250/559.36, 250/559.4, 250/559.44, 250/566, 235/462.32, 235/462.43, 356/71, 414/935-939
• US Class Current: 250/559.44
• CPC Class Codes: B41M 5/262 recording or marking of inorganic surfaces or materials, e.g. glass, metal, or ceramics marking of plastic artifacts with inorganic additives B41M5/267
• CPC Class Codes: H01L 21/67282 Marking devices
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12_t, 12_b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed. The processing system (40) also includes a sensor (36) for sensing identification and orientation information from the wafer edge (E), and a process control computer (46) that receives signals corresponding to the identification information, for purposes of manufacturing data logging and process control.

Claims

1. A system for reading identification information from the edges of semiconductor wafers, comprising:

a wafer carrier, for retaining one or more wafers, and having an opening through which an edge of the one or more wafers retained therein is visible; and

a sensor, for sensing reflected light from an edge of a wafer retained in the wafer carrier.

2. The system of claim 1, further comprising:

a light source, for illuminating a visible edge of a wafer retained within the wafer carrier;

wherein the sensor senses reflected light from the illuminated visible edge of the wafer.

3. The system of claim 2, further comprising:

a motor, for rotating one or more wafers in the wafer carrier into a position at which the sensor may sense reflected light from a marked location along the edge of a wafer.

4. The system of claim 3, further comprising:

a roller, drivably coupled to the motor and in physical contact with the edge of one or more wafers in the carrier.

5. The system of claim 3, wherein the motor is coupled to the sensor, and is responsive to signals from the sensor corresponding to the sensed reflected light.

6. The system of claim 5, wherein orientation information is marked along the edges of the wafers at one or more locations, such orientation information indicative of the relative orientation from a location at which the identification information is marked.