Semiconductor device including a trench with at least one of an edge of an opening and a bottom surface being round

• US 6,710,401 B2
• Filed: 05/11/2000
• Issued: 03/23/2004
• Est. Priority Date: 02/04/1994
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Katsumi, Minato, Tadaharu, Shiozawa, Katsuomi, Tominaga, Shuuichi
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Lee, Eugene
• Application Number:
  US09/569,031
• Publication Number:
  US 20010006836A1
• Time in Patent Office: 1,412 Days
• Field of Search: 438/268, 257/510, 257/302, 257/328, 257/329, 257/330, 257/332
• US Class Current: 257/330
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 : with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device which includes a substrate made of a semiconductor having a main surface. A trench is selectively formed in the substrate at a predetermined depth from the main surface. An insulating film is formed at an inner wall of the trench. A control electrode layer fills an inside of the trench through the insulating film. An insulating layer protrudes from the main surface on the control electrode layer. At least one of an edge of an opening of the trench and a bottom of the trench has a rounded surface.

Claims

1. A semiconductor device, comprising:

a substrate made of semiconductor having a main surface;

a trench selectively formed in said substrate at a predetermined depth from said main surface;

an insulating film formed on an inner wall of said trench;

a control electrode layer filling an inside of said trench through said insulating film, wherein said control electrode layer is used as a MOS gate; and

an insulating layer protruding from said main surface on said control electrode layer,

wherein both of an edge of an opening of said trench and an inner surface of a bottom surface of said trench has a substantially same rounded surface, and

wherein an angle between a line tangent to a surface having a smallest radius of curvature among radiuses of curvature of said rounded surface of said edge of said opening and said main surface ranges from 30°

to 60°

at a section of said edge at said opening.

2. The semiconductor device according to claim 1, wherein

said bottom surface of said trench has a U-shaped configuration.

3. The semiconductor device according to claim 1, wherein

said insulating film further extends over a part of said main surface;

said control electrode layer further extends over said part of said main surface through said insulating film, and

said insulating layer protrudes from said main surface on said control electrode layer in said trench.

4. The semiconductor device according to claim 1, further comprising:

a first semiconductor layer of a conductivity type opposite to that of said substrate and formed at a depth shallower than said predetermined depth in said main surface; and

a second semiconductor layer of the same conductivity type as that of said substrate and formed to be apart from said substrate and adjacent to said opening in said first semiconductor layer.

5. The semiconductor device according to claim 4, further comprising:

a third semiconductor layer of the same conductivity type as that of said substrate and having an impurity concentration higher than that of said substrate and holding said substrate between said third semiconductor layer and said first semiconductor layer.

6. The semiconductor device according to claim 5, further comprising:

a fourth semiconductor layer of the same conductivity type as that of said first semiconductor layer and having an impurity concentration higher than that of said first semiconductor layer and holding said third semiconductor layer between said fourth semiconductor layer and said substrate.

7. The semiconductor device according to claim 4, wherein said trench is a constituent of a mesh on said main surface.

8. The semiconductor device according to claim 7, wherein said trench is a constituent of a lattice on said main surface.

9. The semiconductor device according to claim 4, wherein said trench is a constituent of a plurality of rows on said main surface.

10. The semiconductor device according to claim 1, further comprising:

a first semiconductor layer of a conductivity type opposite to that of said substrate and formed at a depth greater than said predetermined depth in said substrate; and

a second semiconductor layer of the same conductivity type as that of said substrate and formed to be adjacent to said opening in said first semiconductor layer.

11. The semiconductor device according to claim 1, further comprising:

a first semiconductor layer of a conductivity type opposite to that of said substrate and formed at a depth shallower than said predetermined depth in said main surface;

a second semiconductor layer of the same conductivity type as that of said substrate and having an impurity concentration higher than that of said substrate and formed at a depth shallower than said first semiconductor layer in said main surface;

a third semiconductor layer of the same conductivity type as that of said first semiconductor layer and having an impurity concentration higher than that of said first semiconductor layer and formed to be apart from said first semiconductor layer and adjacent to said opening in said second semiconductor layer;

a fourth semiconductor layer of the same conductivity type as that of said second semiconductor layer and having an impurity concentration higher than that of said second semiconductor layer and holding said substrate between said fourth semiconductor layer and said first semiconductor layer; and

a fifth semiconductor layer of the same conductivity type as that of said first semiconductor layer and having an impurity concentration higher than that of said first semiconductor layer and holding said fourth semiconductor layer between said fifth semiconductor layer and said substrate.

12. The semiconductor device according to claim 1, further comprising:

a first semiconductor layer of the same conductivity type as that of said substrate and having an impurity concentration higher than that of said substrate and formed to be adjacent to said opening at a depth shallower than said predetermined depth in said main surface; and

a second semiconductor layer of a conductivity type opposite to that of said substrate and formed to be in contact with said substrate on a side opposite to said main surface.