Vertical MOS transistor and a method of manufacturing the same

• US 6,710,402 B2
• Filed: 06/01/2001
• Issued: 03/23/2004
• Est. Priority Date: 06/02/2000
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Harada, Hirofumi
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US09/872,798
• Publication Number:
  US 20020000608A1
• Time in Patent Office: 1,026 Days
• Field of Search: 257/329-333, 438/270-271, 438/259, 438/587-589
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed are a vertical MOS transistor which lowers the gate resistance, improves the high frequency characteristics, and improves the yield compared with a conventional one and a method of manufacturing the same. When gate voltage is applied to a gate electrode, a channel is formed in a body region along a trench, and electrons or current flow(s) from a drain layer to a source layer. Here, a gate in the trench has a laminated structure of a polycrystalline silicon film and a metal silicide. Therefore, a gate resistance is lowered and the high frequency characteristics are improved. Further, according to the structure and the method of manufacturing, a concave portion generated at an upper portion of the gate in the trench when etching for forming the gate is less liable to be generated, and thus, malfunction and insufficient reliability due to the concave portion can be avoided.

Claims

1. A vertical MOS transistor comprising:

a semiconductor substrate having a first conductivity type;

an epitaxial growth layer having the first conductivity type formed on the semiconductor substrate;

a body region having a second conductivity type formed on the epitaxial growth layer;

a trench having a sidewall extending through the body region of the second conductivity type and having a bottom surface disposed inside of the epitaxial growth layer of the first conductivity type;

a gate insulating film formed of a first gate material and extending along an upper surface of the body region of the second conductivity type and the sidewall and the bottom surface of the trench and having a U-shaped form so as to define a U-shaped void within the trench;

a polycrystalline silicon gate partially filling the internal void of the gate insulating film;

a second gate material comprised of one of a silicon oxide film and a silicon nitride film filling a remaining portion of the internal void not filled by the polycrystalline silicon gate so as to be in contact with the polycrystalline silicon gate and having a sidewall and a bottom surface that are surrounded by the gate insulating film and the polycrystalline silicon gate;

a source region of the first conductivity type formed in the upper surface of the body region of the second conductivity type and around the trench so as to be in contact with the gate insulating film;

a gate electrode connected to the polycrystalline silicon gate and the second gate material;

a source electrode connected to the source region; and

a drain electrode connected to the semiconductor substrate.

2. A vertical MOS transistor according to claim 1;

wherein the first gate material comprises silicon oxide.

3. A vertical MOS transistor according to claim 1;

wherein the trench is formed in a U shape.