Dual trench power MOSFET

• US 6,710,403 B2
• Filed: 07/30/2002
• Issued: 03/23/2004
• Est. Priority Date: 07/30/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sapp, Steven
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US10/209,110
• Publication Number:
  US 20040021173A1
• Time in Patent Office: 602 Days
• Field of Search: 257/330, 257/328, 257/329, 257/341
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductor region, and a source trench which extends into the first semiconductor region. The source trench is laterally spaced from the gate trench.

Claims

1. A MOSFET comprising:

a first semiconductor region of a first conductivity type;

a gate trench extending into the first semiconductor region; and

a source trench extending deeper into the first semiconductor region than the gate trench, the source trench being laterally spaced from the gate trench.

2. The MOSFET of claim 1 further comprising:

a body region in the first semiconductor region between the source trench and the gate trench, the body region being of opposite conductivity type as the first semiconductor region; and

a source region in the body region such that a channel is formed in the body region along a sidewall of the gate trench, the source region being of same conductivity type as the first semiconductor region.

3. The MOSFET of claim 2 wherein:

the gate trench includes conducting material insulated from the first semiconductor region,

the source trench includes conducting material insulated from the first semiconductor material, and

the conductive material in the source trench is coupled to the source region.

4. The MOSFET of claim 3 wherein the conducting material in the gate trench is insulated from the first semiconductor region by an insulating layer having a greater thickness than a thickness of an insulating layer between the conducting material in the gate trench and the channel.

5. The MOSFET of claim 2 further comprising a second semiconductor region of the same conductivity type as the first semiconductor region, the first semiconductor region being over and in contact with the second semiconductor region, the second semiconductor region forming a drain contact region.

6. The MOSFET of claim 5 wherein the MOSFET conducts vertically between the drain region and the source region when in the on state.

7. A method of forming a MOSFET, comprising:

forming a first semiconductor region of a first conductivity type;

forming a gate trench extending into the first semiconductor region; and

forming a source trench extending deeper into the first semiconductor region than the gate trench, the source trench being laterally spaced from the gate trench.

8. The method of claim 7 further comprising:

forming a body region in the first semiconductor region between the source trench and the gate trench, the body region being of opposite conductivity type as the first semiconductor region; and

forming a source region in the body region such that a channel is formed in the body region along a sidewall of the gate trench, the source region being of same conductivity type as the first semiconductor region.

9. The method of claim 8 further comprising:

filling the gate trench with conducting material insulated from the first semiconductor region,

filling the source trench with conducting material insulated from the first semiconductor material, wherein the conductive material in the source trench is coupled to the source region.

10. The method of claim 8 further comprising:

forming a second semiconductor region of the same conductivity type as the first semiconductor region, the first semiconductor region being over and in contact with the second semiconductor region, the second semiconductor region forming a drain contact region.

11. The method of claim 9 wherein the conducting material in the gate trench is insulated from the first semiconductor region by an insulating layer having a greater thickness than a thickness of an insulating layer between the conducting material in the gate trench and the channel.