POWER SEMICONDUCTOR SWITCHING DEVICES, POWER CONVERTERS, INTEGRATED CIRCUIT ASSEMBLIES, INTEGRATED CIRCUITRY, POWER CURRENT SWITCHING METHODS, METHODS OF FORMING A POWER SEMICONDUCTOR SWITCHING DEVICE, POWER CONVERSION METHODS, POWER SEMICONDUCTOR SWITCHING DEVICE PACKAGING METHODS, AND METHODS OF FORMING A POWER TRANSISTOR
DCFirst Claim
1. An integrated circuit assembly comprising:
- a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere;
a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to a surface of the package;
at least one metallization layer coupled with the substrate and configured to couple at least some of the sources in parallel and at least some of the drains in parallel; and
wherein the semiconductive substrate further comprises a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package.
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Abstract
Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides an integrated circuit assembly including a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere; and a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to the surface of the package.
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Citations
50 Claims
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1. An integrated circuit assembly comprising:
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a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere;
a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to a surface of the package;
at least one metallization layer coupled with the substrate and configured to couple at least some of the sources in parallel and at least some of the drains in parallel; and
wherein the semiconductive substrate further comprises a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines a plurality of source contacts and a plurality of drain contacts configured to couple with respective ones of the source contacts and the drain contacts of the package. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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14. An integrated circuit assembly comprising:
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a power semiconductor device comprising;
a semiconductive substrate having a surface; and
a power transistor formed using the substrate and having a plurality of source contacts and drain contacts adjacent to and over substantially an entirety of the surface and configured to conduct power currents;
a package having a plurality of source contacts and a plurality of drain contacts corresponding to and electrically coupled with respective ones of the source contacts and the drain contacts of the power semiconductor device;
at least one metallization layer coupled with the substrate and configured to couple at least some of the source contacts in parallel and at least some of the drain contacts in parallel; and
a horizontal interconnect layer formed upon and coupled with the at least one metallization layer, and the horizontal interconnect layer defines the source contacts and the drain contacts of the power transistor. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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49. An integrated circuit assembly comprising:
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a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere;
a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to a surface of the package; and
a plurality of source electrical interconnects and a plurality of drain electrical interconnects coupled with respective ones of the sources and drains and arranged in alternating columns, and wherein the package comprises a vertical laminate package comprising a plurality of conductive layers corresponding to respective ones of the columns.
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50. An integrated circuit assembly comprising:
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a semiconductive substrate comprising a plurality of field effect transistors having electrically coupled sources and electrically coupled drains comprising regions of the substrate adjacent to a surface of the substrate, and wherein the electrically coupled sources and the electrically coupled drains are collectively configured to conduct power currents in excess of one Ampere;
a package having a plurality of source contacts and a plurality of drain contacts configured to couple with the electrically coupled sources and the electrically coupled drains of the semiconductive substrate, and wherein the source contacts and the drain contacts are provided adjacent to a surface of the package; and
wherein the source contacts and the drain contacts are arranged in a checkerboard pattern.
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Specification