Field emission display having reduced power requirements and method

• US 6,710,538 B1
• Filed: 08/26/1998
• Issued: 03/23/2004
• Est. Priority Date: 08/26/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Patel, Ashok
• Assistant Examiner(s): Guharay, Karabi
• Application Number:
  US09/140,623
• Time in Patent Office: 2,036 Days
• Field of Search: 313/309, 313/310, 313/336, 313/351, 313/495, 313/496, 313/497, 313/311, 445/24, 315/169.1, 438/960
• US Class Current: 313/497
• CPC Class Codes: H01J 1/3044 Point emitters
• CPC Class Codes: H01J 9/025 of field emission cathodes

Abstract

A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer may be formed by oxidation of porous polycrystalline silicon. The display also includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters. The display further includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters. The porous dielectric layer results in columns having less capacitance compared to prior art displays. Accordingly, less electrical power is required to charge and discharge the columns in order to drive the emitters. As a result, the display is able to form luminous images while consuming reduced electrical power compared to prior art displays.

Claims

1. A field emission display baseplate comprising:

a substrate;

a plurality of spaced-apart conductors formed on the substrate;

a plurality of spaced-apart emitter bodies comprising a high resistivity material formed on the conductors;

a porous silicon dioxide dielectric layer formed on the substrate and the conductors by first forming a porous polycrystalline silicon layer having a uniform thickness on the substrate then oxidizing the porous polycrystalline silicon layer to form columnar spacers of silicon dioxide, the porous silicon dioxide layer having respective openings coaxial with the emitter bodies;

an extraction grid formed on the porous silicon dioxide layer and including respective openings coaxial with the emitter bodies; and

an emitter tip formed on each of the emitter bodies in the extraction grid opening, the tip formed from a material having a work function or electron affinity of less than four electron volts.

2. The baseplate of claim 1 wherein the dielectric layer comprises porous silicon dioxide prepared by anodization of polycrystalline silicon followed by oxidation of the anodized polycrystalline silicon.

3. The baseplate of claim 1 wherein the dielectric layer comprises at least 50% voids.

4. The baseplate of claim 1 wherein the dielectric layer has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than three.

5. The baseplate of claim 1 wherein the porous dielectric layer has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than 1.6.

6. The baseplate of claim 1 the dielectric layer comprises porous silicon dioxide prepared by chemical etching of polycrystalline silicon followed by oxidation of the etched polycrystalline silicon.

7. The baseplate of claim 1 wherein the emitter tip comprises a material chosen from a group consisting of:

SiC, Zr, La, Zn, TiN, LaB₆, Ce, Ba, diamond and silicon oxycarbide.

8. The baseplate of claim 1 wherein the emitter body comprises:

silicon monoxide; and

a metal.

9. The baseplate of claim 1 wherein the emitter body comprises:

silicon monoxide; and

less than 10 atomic percent manganese.

10. The baseplate of claim 1 wherein the emitter tip comprises SiC.

11. The baseplate of claim 1 wherein the emitter tip comprises Zr.

12. The baseplate of claim 1 wherein the emitter tip comprises La.

13. The baseplate of claim 1 wherein the emitter tip comprises Zn.

14. The baseplate of claim 1 wherein the emitter tip comprises TiN.

15. The baseplate of claim 1 wherein the emitter tip comprises LaB_6.

16. The baseplate of claim 1 wherein the emitter tip comprises diamond.

17. The baseplate of claim 1 wherein the emitter tip comprises silicon oxycarbide.

18. A field emission display baseplate comprising:

a substrate;

a plurality of conductors formed on the substrate;

a plurality of emitters each formed on one of the plurality of conductors;

a porous silicon dioxide dielectric layer on the substrate and the conductors by first forming a porous polycrystalline silicon layer having a uniform thickness on the substrate then oxidizing the porous polycrystalline silicon layer to form columnar spacers of silicon dioxide;

an extraction grid formed on the dielectric layer and including an opening;

an opening formed in the dielectric layer coaxial with the opening in the extraction grid;

an emitter body comprising a high resistivity material formed in the opening in the porous silicon dioxide layer; and

an emitter tip formed on the emitter body and in the extraction grid opening, the tip formed from a material having a work function or electron affinity of less than four electron volts.

19. The baseplate of claim 18 wherein the porous silicon dioxide comprises porous silicon dioxide prepared by anodization of polycrystalline silicon followed by oxidation of the anodized polycrystalline silicon.

20. The baseplate of claim 18 wherein the porous silicon dioxide comprises at least 50% voids.

21. The baseplate of claim 18 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than three.

22. The baseplate of claim 18 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than 1.6.

23. The baseplate of claim 18, wherein the porous silicon dioxide comprises porous silicon dioxide prepared by chemical etching of polycrystalline silicon followed by oxidation of the etched polycrystalline silicon.

24. A field emission display baseplate comprising:

a substrate;

a plurality of spaced-apart conductors formed on the substrate;

a porous silicon dioxide layer formed on the substrate and the conductors by first forming a porous polycrystalline silicon layer having a uniform thickness on the substrate then oxidizing the porous polycrystalline silicon layer to form columnar spacers of silicon dioxide;

an extraction grid formed on the porous silicon dioxide layer and including an opening;

an opening formed in the porous silicon dioxide layer coaxial with the opening in the extraction grid; and

an emitter formed in the opening in the porous silicon dioxide layer and in the extraction grid opening.

25. The baseplate of claim 24 wherein the porous silicon dioxide layer comprises silicon dioxide prepared by anodization of polycrystalline silicon followed by oxidation of the anodized polycrystalline silicon.

26. The baseplate of claim 24 wherein the porous silicon dioxide comprises at least 50% voids.

27. The baseplate of claim 24 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than three.

28. The baseplate of claim 24 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than 1.6.

29. The baseplate of claim 24 wherein the porous silicon dioxide comprises silicon dioxide prepared by chemical etching of silicon to provide porous silicon followed by oxidation the porous silicon.

30. The baseplate of claim 24 wherein emitter comprises:

an emitter body comprising a high resistivity material; and

an emitter tip formed on the emitter body and in the extraction grid opening.

31. The baseplate of claim 30 wherein the emitter tip comprises a material chosen from a group consisting of:

SiC, Zr, La, Zn, TiN, LaB₆, Ce, Ba, diamond and silicon oxycarbide.

32. The baseplate of claim 30 wherein the emitter body comprises:

silicon monoxide; and

a metal.

33. The baseplate of claim 30 wherein the emitter body comprises:

silicon monoxide; and

less than 10 atomic percent manganese.

34. The baseplate of claim 30 wherein the emitter tip comprises a material chosen from a group consisting of:

SiC, Zr, La;

Zn, TiN, LaB₆, diamond and silicon oxycarbide.

35. A field emission display comprising:

a substrate;

a plurality of emitters formed on the substrate, each of the emitters being formed on a conductor;

a porous dielectric layer formed on the substrate by first forming a porous polycrystalline silicon layer having a uniform thickness on the substrate then oxidizing the porous polycrystalline silicon layer to form columnar spacers of silicon dioxide, the porous dielectric layer having an opening formed about each of the emitters, the porous dielectric layer having a thickness substantially equal to a height of the emitters above the substrate, the porous layer formed by oxidation of porous silicon;

an extraction grid extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters and having an opening surrounding each tip of a respective one of the emitters; and

a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters.

36. The display of claim 35 wherein the porous silicon dioxide comprises at least 50% voids.

37. The display of claim 35 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than three.

38. The display of claim 35 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than 1.6.

39. The display of claim 35 wherein the porous silicon is formed by anodization of a polycrystalline silicon layer.

40. The display of claim 35 wherein each of the emitters comprise:

an emitter body comprising a high resistivity material; and

an emitter tip formed on the emitter body and in the extraction grid opening.

41. The display of claim 40 wherein:

the emitter tips each comprise a material chosen from a group consisting of;

SiC, Zr, La, Zn, TiN, LaB₆, Ce, Ba, diamond and silicon oxycarbide; and

the emitter bodies each comprise a cermet material.

42. The baseplate of claim 40 wherein the emitter bodies each comprise:

silicon monoxide; and

less than 10 atomic percent metal.

43. The display of claim 40 wherein:

the emitter tips each comprise a material chosen from a group consisting of;

SiC, Zr, La, Zn, TiN, LaB₆, diamond and silicon oxycarbide; and

the emitter bodies each comprise a cermet material.

44. A computer system comprising:

a central processing unit;

a memory device coupled to the central processing unit, the memory device storing instructions and data for use by the central processing unit;

a input interface; and

a display, the display comprising;

a cathodoluminescent layer formed on a conductive surface of a transparent faceplate;

a substrate disposed parallel to and near the cathodoluminescent layer formed on the faceplate;

a plurality of conductors formed on the substrate;

a plurality of emitters formed on the conductors;

a porous silicon dioxide layer formed on the substrate and the conductors, the porous silicon dioxide layer including openings each formed about one of the emitters, the porous layer formed by first forming a porous polycrystalline silicon layer having a uniform thickness on the substrate then oxidizing the porous silicon layer to form columnar spacers of silicon dioxide; and

an extraction grid formed on the porous silicon dioxide layer and including openings each coaxial with one of the openings in the porous silicon dioxide layer.

45. The computer system of claim 44, wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than three.

46. The computer system of claim 44 wherein the porous silicon dioxide has about 22.5 to about 61.5 percent voids and a relative dielectric constant of less than 1.6.

47. The computer system of claim 44 wherein the porous silicon is formed by anodization of a polycrystalline silicon layer.

48. The computer system of claim 44 wherein each of the emitters comprises:

an emitter body comprising a high resistivity material; and

an emitter tip formed on the emitter body and in the extraction grid opening.

49. The computer system of claim 48 wherein:

the emitter tips each comprise a material chosen from a group consisting of;

SiC, Zr, La, Zn, TiN, LaB₆, Ce, Ba, diamond and silicon oxycarbide; and

the emitter bodies each comprise a cermet material.

50. The computer system of claim 48 wherein the emitter bodies each comprise:

silicon monoxide; and

less than 10 atomic percent metal.

51. The computer system of claim 48 wherein tips of the emitters are formed from materials having a work function of less than four electron volts.