Non-overlap clock circuit

• US 6,710,637 B1
• Filed: 04/29/2002
• Issued: 03/23/2004
• Est. Priority Date: 04/29/2002
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Chan, Wai Cheong
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US10/134,832
• Time in Patent Office: 694 Days
• Field of Search: 327/259, 327/231, 327/258, 327/239, 327/237
• US Class Current: 327/259
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/1515 non-overlapping
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

Claims

1. A non-overlap clock circuit providing two non-overlapping clock outputs, comprising

a first flip-flop having a non-inverted output, providing a first clock output from its non-inverted output,

a second flip-flop having an inverted output providing a second clock output from its inverted output, wherein the first flip-flop and second flip-flop are triggered by a common input clock signal and are set up to toggle in response to the input clock signal,

a first feedback loop from the first clock output to control the triggering of the second flip-flop, and

a second feedback loop from the second clock output to control the triggering of the first flip-flop.

2. A circuit of claim 1, wherein the first and second feedback loops include programmable delay circuits.

3. A circuit of claim 2, wherein each programmable delay circuit comprises a set of flip-flops defining a delay path, with the output of each previous flip-flop feeding the clock input of the next flip-flop, each flip-flop introducing a propagation delay through the flip-flop, the circuit further comprising means for selecting any number of the flip-flops for inclusion in the delay path.

4. A circuit of claim 3, wherein the outputs of the flip-flops of the delay circuit are connected together using transmission gates, and wherein said flip-flops are selected for inclusion in the delay path by selecting the corresponding transmission gates using control logic.

5. A circuit of claim 1, further including an edge detector providing the common input clock signal.

6. A method of generating two clock signals while preventing the overlap of either the low or high portions of the two clock signals, comprising

feeding an incoming clock signal through two cross-coupled clock-generator flip flops that are cross coupled by means of two feedback loops,

tapping off two clock signals from the clock-generator flip-flops, and

selectively delaying each of the tapped-off clock signals by means of delay lines, wherein each delay line comprises at least one flip-flop, the number of flip-flops in each delay line being selectable.

7. A method of claim 6, wherein one of said delay lines is included in each of the feedback loops.

8. A method of claim 7, wherein at least one of the delay lines includes a plurality of flip-flops that are programmably selected for inclusion in the delay line.

9. A method of claim 8, wherein the incoming clock signal is established by feeding an originating clock signal through an edge detector to provide an incoming clock signal of twice the frequency of the originating clock signal.