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Acoustic noise suppressing circuit by selective enablement of an interpolator

  • US 6,710,725 B1
  • Filed: 04/12/1999
  • Issued: 03/23/2004
  • Est. Priority Date: 04/12/1999
  • Status: Active Grant
First Claim
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1. A signal processor circuit comprising:

  • a buffer for storing digital data samples, the digital data samples being selectively formatted in a plurality of data formats; and

    a circuit for eliminating format-dependent transients in a signal processor coupled to the buffer including;

    a sample formatter coupled to the buffer for receiving digital data samples from the buffer and selectively modifying digital data samples from a first data format to a second data format of the plurality of data formats;

    an interpolator coupled to the sample formatter; and

    a control logic coupling the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer.

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