Acoustic noise suppressing circuit by selective enablement of an interpolator

• US 6,710,725 B1
• Filed: 04/12/1999
• Issued: 03/23/2004
• Est. Priority Date: 04/12/1999
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc., Seppi M. S.R.L.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Soques, Martin P.
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US09/290,048
• Time in Patent Office: 1,807 Days
• Field of Search: 341/143, 341/61, 327/270, 327/551, 327/310, 330/51, 348/580, 348/478, 710/57, 375/295, 708/316, 708/320, 708/628, 361/110, 714/743, 704/265, 381/94.1
• US Class Current: 341/61
• CPC Class Codes: H03G 3/345 Muting during a short period of time when noise pulses are detected, i.e. blanking H03G3/348 takes precedence
• CPC Class Codes: H03G 3/348 Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits

Abstract

Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats. The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats. The circuit for eliminating format-dependent transients also includes an interpolator coupled to the sample formatter and a control logic connecting the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer.

Claims

1. A signal processor circuit comprising:

a buffer for storing digital data samples, the digital data samples being selectively formatted in a plurality of data formats; and

a circuit for eliminating format-dependent transients in a signal processor coupled to the buffer including;

a sample formatter coupled to the buffer for receiving digital data samples from the buffer and selectively modifying digital data samples from a first data format to a second data format of the plurality of data formats;

an interpolator coupled to the sample formatter; and

a control logic coupling the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer.

2. A signal processor circuit according to claim 1 wherein the control logic includes:

a shift register coupled to receive a driving signal from the buffer and coupled to receive a formatting done signal from the sample formatter, the shift register generating a control signal; and

a gate circuit coupled to transfer the digital data samples from the sample formatter to the interpolator, the gate circuit being enabled and disabled by the control signal.

3. A signal processor circuit according to claim 1 wherein:

the sample formatter converts formatting of digital data samples between 8-bit samples and 16-bit samples.

4. A signal processor circuit according to claim 1 wherein:

the sample formatter converts formatting of digital data samples between 8-bit samples and 16-bit samples, the 8-bit samples being selected from among an unsigned format, a μ

-law format, and an A-law format.

5. A signal processor circuit according to claim 1 wherein:

the buffer is coupled to a data bus, the data bus supplying digital data samples to the buffer.

6. A signal processor circuit according to claim 1 wherein:

the buffer and the circuit for eliminating format-dependent transients in an audio signal processor form an acoustic playback pathway.

7. An audio signal processor circuit comprising:

a first-in-first-out (FIFO) buffer that stores digital data samples, the digital data samples being selectively formatted in a plurality of data formats;

a digital-to-analog converter (DAC) coupled to the FIFO buffer that converts the digital data samples into analog signals; and

a circuit that eliminates format-dependent transients in an audio signal processor coupling the FIFO buffer to the DAC including;

a sample formatting block coupled to the FIFO buffer that receives digital data samples from the FIFO buffer and selectively modifies digital data samples from a first data format to a second data format of the plurality of data formats;

an interpolator coupled to the sample formatting block; and

an enable/disable logic coupling the sample formatting block to the interpolator that disables transfer of digital data samples from the sample formatting block to the interpolator during changes between data formats, and otherwise enables transfer.

8. An audio signal processor circuit according to claim 7 wherein the enable/disable logic includes:

a shift register driven by a sample available signal from the FIFO buffer, clocked by a formatting done signal from the sample formatting block, and generating an enable/disable signal; and

a multiple-element bank of gates coupled to transfer the digital data samples from the sample formatting block to the interpolator, the gates being enabled and disabled by the enable/disable signal.

9. An audio signal processor circuit according to claim 7 wherein:

the sample formatting block converts formatting of digital data samples between 8-bit samples and 16-bit samples.

10. An audio signal processor circuit according to claim 7 wherein:

the sample formatting block converts formatting of digital data samples between 8-bit samples and 16-bit samples, the 8-bit samples being selected from among an unsigned format, a μ

-law format, and an A-law format.

11. An audio signal processor circuit according to claim 7 wherein:

the FIFO buffer is coupled to a data bus, the data bus supplying digital data samples to the FIFO buffer.

12. An audio signal processor circuit according to claim 7 wherein:

the FIFO buffer, the DAC, and the circuit that eliminates format-dependent transients in an audio signal processor form an acoustic playback pathway.

13. A coder-decoder (CODEC) comprising:

a receive pathway circuit including an analog-to-digital converter (ADC), a receive format converter coupled to the ADC, and a receive buffer coupled to the receive format converter;

a playback pathway circuit including;

a playback buffer for storing digital data samples, the digital data samples being selectively formatted in a plurality of data formats; and

a circuit for eliminating format-dependent transients in a signal processor coupled to the playback buffer including;

a sample formatter for receiving digital data samples from the playback buffer and selectively modifying digital data samples from a first data format to a second data format of the plurality of data formats;

an interpolator coupled to the sample formatter; and

a control logic coupling the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer; and

a mixer coupled to the receive pathway circuit and the playback pathway circuit.

14. A CODEC according to claim 13 wherein the control logic includes:

a shift register coupled to receive a driving signal from the playback buffer and coupled to receive a formatting done signal from the sample formatter, the shift register generating a control signal; and

a gate circuit coupled to transfer the digital data samples from the sample formatter to the interpolator, the gate circuit being enables and disabled by the control signal.

15. A computer system comprising:

a processor;

a memory coupled to the processor;

a bus coupled to the processor; and

a coder-decoder (CODEC) comprising;

a receive pathway circuit including an analog-to-digital converter (ADC), a receive format converter coupled to the ADC, and a receive buffer coupled to the receive format converter;

a playback pathway circuit including;

a playback buffer for storing digital data samples, the digital data samples being selectively formatted in a plurality of data formats; and

a circuit for eliminating format-dependent transients in a signal processor coupled to the playback buffer including;

a sample formatter coupled to the playback buffer for receiving digital data samples from the playback buffer and selectively modifying digital data samples from a first data format to a second data format of the plurality of data formats;

an interpolator coupled to the sample formatter; and

a control logic coupling the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer; and

a mixer coupled to the receive pathway circuit and the playback pathway circuit.

16. A computer system according to claim 15 wherein the control logic includes:

a shift register coupled to receive a driving signal from the playback buffer and coupled to receive a formatting done signal from the sample formatter, the shift register generating a control signal; and

a gate circuit coupled to transfer the digital data samples from the sample formatter to the interpolator, the date circuit being enabled and disabled by the control signal.

17. A method of eliminating format-dependent transients in a signal processor comprising:

accessing digital data samples that are selectively formatted in a plurality of data formats;

selectively modifying the format of digital data samples from a first data format to a second data format of the plurality of data formats;

interpolating the accessed digital data samples; and

disabling interpolation of the digital data samples during changes between data formats, and otherwise enabling interpolation.

18. A method according to claim 17, further comprising:

storing a plurality of the accessed digital data samples; and

determining when a sample is available from the stored digital data samples.

19. A method according to claim 18, further comprising:

determining when the selective modification of the digital data samples is complete; and

determining whether the interpolation is to be enabled or disabled by delaying interpolation until the available sample by a delay time clocked by completion of the selective modification of the digital data samples.

20. A signal processor circuit comprising:

a buffer for storing digital data samples, the digital data samples being selectively formatted in a plurality of data formats; and

means for eliminating format-dependent transients in a signal processor coupled to the buffer including;

means coupled to the buffer for receiving digital data samples from the buffer and selectively modifying digital data samples from a first data format to a second data format of the plurality of data formats;

means coupled to the modifying means for interpolating samples; and

means coupling the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer.

21. A signal processor circuit according to claim 20 wherein the means for disabling and enabling transfer includes:

means coupled to receive a driving signal from the buffer and coupled to receive a formatting done signal from the sample formatter for generating a control signal; and

a gate circuit coupled to transfer the digital data samples from the modifying means to the interpolating means, the gate circuit being enabled and disabled by the control signal.