Three-dimensional memory cache system

• US 6,711,043 B2
• Filed: 06/27/2002
• Issued: 03/23/2004
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Tringali, J. James, Friedman, David R., Schneider, James E., Steere, Daniel C., Scheuerlein, Roy E., Moore, Christopher S.
• Primary Examiner(s): Lam, David
• Application Number:
  US10/186,356
• Publication Number:
  US 20020167829A1
• Time in Patent Office: 635 Days
• Field of Search: 365/51, 365/52, 365/63, 365/130, 365/185.04, 365/104, 365/94, 361/735, 361/803
• US Class Current: 365/51
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Claims

1. A modular memory device removably connectable to a host device, the modular memory device comprising:

a substrate;

a cache memory array;

a three-dimensional primary memory array comprising a plurality of layers of memory cells stacked vertically above one another and above the substrate; and

a modular housing enclosing the substrate, cache memory array, and three-dimensional primary memory array.

2. The invention of claim 1, wherein the cache memory array comprises a plurality of volatile memory cells and the three-dimensional primary memory array comprises a plurality of non-volatile memory cells, wherein the three-dimensional primary memory array has a greater storage capacity than the cache memory array, and wherein memory cells of the three-dimensional primary memory array have a slower access time than memory cells of the cache memory array.

3. The invention of claim 1, wherein the cache memory array is formed in the substrate under the three-dimensional primary memory array.

4. The invention of claim 1 further comprising a second substrate enclosed by the modular housing, wherein the cache memory array is formed in the second substrate.

5. The invention of claim 1 further comprising control logic coupled with the three-dimensional primary memory array and the cache memory array.

6. The invention of claim 5, wherein the control logic is responsible for flow control.

7. The invention of claim 5, wherein the control logic is coupled with a processing unit in a host device via a flow control bus, and wherein the control logic is operative to send a wait signal to the processing unit via the flow control bus if data requested by the processing unit is not stored in the cache memory array.

8. The invention of claim 5, wherein the control logic is coupled with a processing unit in a host device, and wherein the processing unit is operative to perform a task while waiting for data requested by the processing unit to be transferred from the three-dimensional primary memory array to the cache memory array.

9. The invention of claim 8, wherein the control logic is operative to send an interrupt signal in a sideband of a data bus coupling the control logic and the processing unit after the data requested by the processing unit is transferred from the three-dimensional primary memory array to the cache memory array.

10. The invention of claim 5, wherein the control logic is operative to send a processing unit in a host device a set of instructions in lieu of data requested by the processing unit if the data requested by the processing unit is not stored in the cache memory array.

11. The invention of claim 5, wherein the control logic comprises a DMA controller.

12. The invention of claim 1, wherein a host device connected to the modular memory device is responsible for flow control between the three-dimensional primary memory array and the cache memory array.

13. The invention of claim 1, wherein the three-dimensional primary memory array comprises a plurality of write-once memory cells.

14. The invention of claim 1, wherein the three-dimensional primary memory array comprises a plurality of write-many memory cells.

15. The invention of claim 1, wherein the three-dimensional primary memory array comprises a semiconductor memory array.

16. An integrated circuit comprising:

a substrate;

a cache memory array formed in the substrate; and

a three-dimensional primary memory array comprising a plurality of layers of memory cells stacked vertically above one another and above the substrate.

17. The invention of claim 16, wherein the integrated circuit further comprises control logic operative to transfer data between the cache memory array and the three-dimensional primary memory array.

18. The invention of claim 16, wherein the cache memory array and the three-dimensional primary memory array are in communication with control logic external to the integrated circuit, the control logic operative to transfer data between the cache memory array and the three-dimensional primary memory array.

19. The invention of claim 17 or 18, wherein the control logic is in communication with a processing unit, and wherein the control logic is operative to store data received from the processing unit in the cache memory array and then transfer the data from the cache memory array to the three-dimensional primary memory array.

20. The invention of claim 17 or 18, wherein the control logic is in communication with a processing unit, and wherein the control logic is operative to transfer data stored in the three-dimensional primary memory array to the cache memory array and then transfer the data from the cache memory array to the processing unit.

21. The invention of claim 16, wherein the cache memory array comprises a plurality of volatile memory cells and the three-dimensional primary memory array comprises a plurality of non-volatile memory cells, wherein the three-dimensional primary memory array has a greater storage capacity than the cache memory array, and wherein memory cells of the three-dimensional primary memory array have a slower access time than memory cells of the cache memory array.

22. The invention of claim 16, wherein the cache memory array comprises SRAM memory cells.

23. The invention of claim 16, wherein the cache memory array comprises DRAM memory cells.

24. The invention of claim 16, wherein the three-dimensional primary memory array comprises anti-fuse memory cells.

25. The invention of claim 16, wherein the three-dimensional primary memory array comprises EEPROM memory cells.

26. The invention of claim 16, wherein at least some memory cells of the cache memory array are pitch-matched to at least some memory cells of the three-dimensional primary memory array.

27. The invention of claim 16, wherein the integrated circuit is part of a disk drive controller.

28. The invention of claim 16, wherein the integrated circuit is part of a modular memory device that is removably connectable to a host device.

29. The invention of claim 16 further comprising support circuitry for the three-dimensional primary memory array, the support circuitry formed in the substrate at least partially under the three-dimensional primary memory array, wherein the support circuitry defines open area in the substrate under the three-dimensional primary memory array, and wherein the cache memory array is formed at least partially in the open area in the substrate under the three-dimensional primary memory array.