Static RAM architecture with bit line partitioning

• US 6,711,051 B1
• Filed: 09/05/2002
• Issued: 03/23/2004
• Est. Priority Date: 09/05/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Lum, Annie-Li-Keow, Franklin, Andrew J., Poplevine, Pavel, Zhang, Weipeng
• Primary Examiner(s): Lam, David
• Application Number:
  US10/235,530
• Time in Patent Office: 565 Days
• Field of Search: 365/154, 365/203, 365/189.02, 365/189.01, 365/207
• US Class Current: 365/154
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A SRAM system which provides for reduced power consumption. The SRAM system utilizes an array of bit cells. Columns of bit cells in the array are partitioned into sections. Each section of bit cells shares a local bit line. A sector select circuit provides for precharging the local bit lines. The sector select circuit also includes a mux for connecting a local bit line to a global bit line. The sector select circuit includes a device for detecting when a sector select signal and a column select signal are present. When both of these signals are present the sector select circuit couples the local bit line with the global bit line, and disengages the precharging of the local bit line.

Claims

1. A SRAM memory system for storing data, including:

a plurality of columns of bit cells, wherein the columns of bit cells are partitioned into a plurality of sectors of bit cells;

a plurality of sector select circuits;

a plurality of local bit lines, wherein a sector of bit cells is coupled to a sector select circuit by a local bit line;

a plurality of global bit lines, wherein a global bit line is coupled to the sector select circuit; and

wherein the sector select circuit includes a switch which couples the local bit line with the global bit line so that a selected bit cell in the sector of bit cells can be read from, or written to.

2. The SRAM memory system of claim 1, wherein the sector select circuit includes an input for receiving a column select signal, and an input for receiving a sector select signal, and includes a circuit for generating a local column select signal based on a received column select signal and a received sector select signal.

3. The SRAM memory system of claim 1, further including a local column select line coupling the sector select circuit with the sector of bit cells, such that each bit cell of the of the sector of bit cells receives a local column select signal generated by the sector select circuit.

4. The SRAM memory system of claim 1, wherein the sector select circuit includes an input for receiving a column select signal, and an input for receiving a sector select signal, and includes a circuit for generating a local column select signal based on a received column select signal and a received sector select signal, and the SRAM memory system further includes a local column select line coupling the sector select circuit with the sector of bit cells, such that each bit cell of the of the sector of bit cells receives the local column select signal.

5. The SRAM system of claim 4, further including:

a plurality of word line pass gate transistors, wherein a word line pass transistor is coupled to a bit cell of the sector of bit cells;

a plurality of word lines wherein a word line is coupled to a word line pass gate transistor;

wherein a bit cell of the sector of bit cells include a column select pass gate transistor;

wherein the local column select line is coupled to the column select pass gate transistor of the bit cell, such that when a local column select signal is present on the local column select line the column select pass gate transistor is open, and wherein a when signal is present on the word line the word line pass gate transistor is open, and wherein when both the word line pass gate transistor and the column select pass gate transistor are open data can be read from or written to the bit cell.

6. The SRAM system of claim 1, wherein the sector select circuit includes a precharge circuit coupled to the local bit line, wherein the precharge circuit precharges the local bit line.

7. A sector select circuit for use in a SRAM system having a plurality of local bit lines and a plurality of global bit lines, the sector select circuit, including:

a mux circuit for coupling a local bit line of the SRAM with a global bit line of the SRAM system;

a first input for receiving a column select signal form the SRAM system;

a second input for receiving a sector select signal from the SRAM system;

a local column select signal circuit which generates a local column select signal in response to receiving a sector select signal and a column select signal,

wherein the mux circuit is coupled to the local column select signal circuit, and in response to a local column select signal, the mux couples the local bit with the with the global bit line.

8. The sector select circuit of claim 7, further including an AND gate which receives a select signal from the first input and an sector select signal from the second input, and when both of these signals are present outputs a signal to the mux circuit which causes the mux to couple the local bit line with the global bit line.

9. The sector select circuit of claim 7, further including an input for receiving a it line select signal from an adjacent sector select circuit, the mux circuit is coupled to the input for receiving the line select signal such that in response to the line select signal the mux couples the local bit line with the global bit line.

10. The sector select circuit of claim 7, wherein the mux includes an NMOS transistor which is coupled to the local column select signal circuit such that the NMOS transistor opens, in response to a local column select signal, whereby the local bit line is coupled to the global bit line when the NMOS transistor is open.

11. The sector select circuit of claim 7, further including a precharge circuit for precharging the local bit line.

12. The sector select circuit of claim 11, wherein the precharge circuit includes a first transistor which is coupled to local column select signal circuit such that in response to a local column select signal, the first transistor is closed, whereby when the transistor is closed the precharge circuit does not apply a precharge voltage to the local bit line.

13. The sector select circuit of claim 12, further including an input for receiving a line select signal from an adjacent sector select circuit, wherein the precharge circuit includes a second transistor which is coupled to the select signal from the adjacent sector select signal such that in response to the a line select signal the second transistor is closed, whereby when the second transistor is closed the precharge circuit does not apply a precharge voltage to the local bit line.

14. A SRAM system for storing data including:

an array of bit cells including columns and rows of bit cells;

wherein the columns of bit cells are partitioned into sectors of bit cells, and form an array of columns and rows of sectors of bits cells;

a plurality of local bit lines, wherein bit cells of a sector of bit cells are coupled to a local bit line;

an array of sector selection circuits including columns and rows of sector selection circuits wherein the array of sector selection circuits corresponds the array of columns and rows of sectors of bit cells, and wherein a sector selection circuit is coupled to the local bit line coupled to bit cells of the sector of bit cells;

a plurality of column select lines, wherein a column select line is coupled to a column of sector selection circuits;

a plurality of sector selection lines, wherein a sector selection line is coupled to a row of sector selection circuits;

a plurality of global bit lines, wherein a global bit line is coupled to the column of sector selection circuits; and

wherein a sector selection circuit includes a first circuit and a switch, wherein the first circuit detects when a sector selection signal is present on the sector selection line and when a column selection signal is present on the column selection line and when both signals are present closes the switch whereby a local bit line is coupled with a global bit line.

15. The SRAM system of claim 14, further including:

a plurality of local column select lines, wherein the sector select circuit is coupled to the sector of bit cells by a local column select line;

wherein the bit cells in the sectors of bit cells include a column select pass gate transistor;

wherein when the first circuit of the sector selection circuit detects a sector selection signal and a column selection signal, the first circuit transmits a local column select signal on the local column select line which causes the column select pass gate transistor to open.

16. The SRAM system of claim 15, wherein the fist circuit includes and AND gate which outputs the local column select signal when the sector select signal and column select signal are present.

17. The SRAM system of claim 16, further including:

a plurality of rows of word line pass gate transistors, wherein a wordline pass gate transistor is coupled to a local bit line and a bit cell;

a plurality of word lines, wherein a word line is coupled to a row of word line pass gate transistors, such that when a signal is present on the word line, word line pass gate transistors of the row of word line pass gate transistors are opened.

18. The SRAM system of claim 14, wherein a first column of sectors of bit cells, and a second column of sectors of bits cells share a local bit line.