Structures and methods for direct conversion from radio frequency modulated signals to baseband signals

• US 6,711,397 B1
• Filed: 11/20/2000
• Issued: 03/23/2004
• Est. Priority Date: 11/20/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: ON Semiconductor Corporation
• Inventors: Christensen, Craig L., Petrov, Andrei R., Reinhard, Kenneth L.
• Primary Examiner(s): Nguyen, Duc M.
• Application Number:
  US09/716,305
• Time in Patent Office: 1,219 Days
• Field of Search: 455/324, 455/326, 455/303, 455/304, 455/305, 455/306, 455/310, 455/313, 455/317, 455/296, 363/136, 363/124, 363/138, 363/43, 375/261, 375/318, 375/319, 375/320, 375/328, 375/324
• US Class Current: 455/324
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A direct conversion receiver is disclosed that converts RF signal into corresponding quadrature baseband signals without requiring conversion through an intermediate frequency. The direct conversion receiver abates local oscillator leakage, increases dynamic range and increases RF selectivity as compared to conventional direct conversion circuits. The circuit includes an in-phase branch and a quadrature-phase branch, each branch including two mixers instead of the conventional one. Each mixer is provided with balanced control signals that include a primary control signal and a complementary control signal. For each branch, the signals from the mixer pass through an operational amplifier and a low pass filter to extract the corresponding baseband signal component.

Claims

1. A direct conversion receiver for converting a radio frequency modulated signal into a corresponding baseband signal without requiring conversion through an intermediate frequency while abating local oscillator leakage, increasing dynamic range and increasing RF selectivity, the direct conversion circuit comprising the following:

an oscillator component configured to generate a plurality of binary control signals, each binary control signal having a frequency substantially equal to the radio carrier frequency of the radio frequency modulated signal or substantially equal to the odd subharmonic of the radio frequency modulated signal, the plurality of binary control signals including the following;

a first binary control signal that has a duty cycle of approximately twenty-five percent of the radio frequency modulated signal where the first binary control signal is high;

a first complement binary control signal that is the approximate complement of the first binary control signal;

a second binary control signal that is approximately 180 degrees out of phase with the first binary control signal and that has a duty cycle of approximately twenty-five percent of the radio frequency modulated signal where the second binary control signal is high; and

a second complement binary control signal that is the approximate complement of the second binary control signal;

a plurality of switches, each switch having an input, an output, and control terminals, each switch configured to pass the radio frequency modulated signal from its input terminal to its output terminal according to the control signals on its control terminals, the plurality of switches comprising the following;

a first switch configured to receive at its control terminals the first binary control signal and the first complement binary control signal; and

a second switch configured to receive at its control terminals the second binary control signal and the second complement binary control signal.

2. The direct conversion receiver in accordance with claim 1,

wherein the plurality of binary control signals further include the following:

a third binary control signal that is approximately 90 degrees out of phase with the first binary control signal and that has a duty cycle of approximately twenty-five percent of the radio frequency modulated signal where the third binary control signal is high;

a third complement binary control signal that is the approximate complement of the third binary control signal;

a fourth binary control signal that is approximately 270 degrees out of phase with the first binary control signal and that has a duty cycle of approximately twenty-five percent of the radio frequency modulated signal where the fourth binary control signal is high; and

a fourth complement binary control signal that is the approximate complement of the fourth binary control signal,

and wherein the plurality of switches further comprises the following;

a third switch configured to receive at its control terminals the third binary control signal and the third complement binary control signal; and

a fourth switch configured to receive at its control terminals the fourth binary control signal and the fourth complement binary control signal.

3. The direct conversion circuit in accordance with claim 1, wherein the first switch comprises the following:

a first single pole single throw (SPST) switch coupled between the input terminal and a common node of the first switch, the first SPST switch configured to receive the first binary control signal so as to close when the first binary control signal is high;

a second SPST switch coupled between the common node and the output terminal of the first switch, the second SPST switch configured to receive the first binary control signal so as to close when the first binary control signal is high, wherein the input terminal of the first switch is connected to the output terminal of the first switch through the first and second SPST switches when the first binary control signal is high; and

a first shunt SPST switch coupled between the common node and a voltage source of the first switch, the shunt SPST configured to receive the first complementary binary control signal so as to close when the first complementary binary control signal is high.

4. The direct conversion circuit in accordance with claim 3, wherein the second switch comprises the following:

a third single pole single throw (SPST) switch coupled between the input terminal and a common node of the second switch, the third SPST switch configured to receive the second binary control signal so as to close when the second binary control signal is high;

a fourth SPST switch coupled between the common node and the output terminal of the second switch, the fourth SPST switch configured to receive the second binary control signal so as to close when the second binary control signal is high, wherein the input terminal of the second switch is connected to the output terminal of the second switch through the third and fourth SPST switches when the second binary control signal is high; and

a second shunt SPST switch coupled between the common node and a voltage source of the second switch, the shunt SPST switch configured to receive the second complement binary control signal so as to close when the second complement binary control signal is high.

5. The direct conversion circuit in accordance with claim 3, wherein the first and second SPST switches and the first shunt SPST switch are nMOS transistors.

6. The direct conversion circuit in accordance with claim 1, wherein the first switch comprises the following:

at least a first, second and third SPST switch coupled in series between the input terminal and the output terminal of the first switch, wherein the control terminal of each of the at least first, second and third SPST switch is configured to receive the first binary control signal so as to close and couple the input terminal of the first switch to the output terminal of the first switch when the first binary control signal is high; and

a shunt SPST switch coupled between at least one of the common nodes and a voltage source of the first switch, wherein the shunt SPST switch is configured to receive the first complement binary control signal so as to close when the first complement binary control signal is high.

7. The direct conversion circuit in accordance with claim 6, wherein the first, second and third SPST switches and the shunt SPST switch are nMOS transistors.

8. The direct conversion circuit in accordance with claim 1, further comprising an amplifier for amplifying the radio frequency modulated signal prior to being forwarded to the plurality of switches.

9. The direct conversion circuit in accordance with claim 1, further comprising an antenna for receiving the radio frequency modulated signal prior to being forwarded to the plurality of switches.

10. The direct conversion circuit in accordance with claim 1, further comprising signal processing circuitry.

11. The direct conversion circuit in accordance with claim 10, wherein the signal processing circuitry controls the timing of the plurality of binary control signals.

12. A direct conversion receiver in accordance with claim 1, further comprising the following:

a first operational amplifier having input terminals coupled to the output terminals of the first and second switches; and

a first low pass filter having an input terminal coupled to the output terminal of the first operational amplifier and configured to output a first baseband signal.

13. A direct conversion receiver for converting a radio frequency modulated signal into a corresponding baseband signal without requiring conversion through an intermediate frequency while abating local oscillator leakage, increasing dynamic range and increasing RF selectivity, the direct conversion circuit comprising the following:

an antenna configured to receive the radio frequency modulated signal;

an amplifier configured to receive and amplify the radio frequency modulated signal received by the antenna;

an oscillator component configured to generate a plurality of control signals, each control signal having a frequency substantially equal to the radio carrier period of the radio frequency modulated signal or substantially equal to the odd subharmonic of the radio frequency modulated signal, the plurality of control signals including the following;

a first control signal;

a first complement control signal;

a second control signal that is approximately 180 degrees out of phase with the first control signal;

a second complement control signal;

a third control signal that is approximately 90 degrees out of phase with the first control signal;

a third complement control signal;

a fourth control signal that is approximately 270 degrees out of phase with the first control signal; and

a fourth complement control signal,

a plurality of mixers, each mixer having an input, an output, and control terminals, each mixer configured to receive the radio frequency modulated signal from the amplifier and pass the radio frequency modulated signal from its input terminal to its output terminal according to the signals on its control terminals, the plurality of mixers comprising the following;

a first mixer configured to receive at its control terminals the first control signal and the first complement control signal, wherein the first mixer comprises the following;

a first nMOS transistor coupled between the input terminal and a common node of the first mixer, the first nMOS transistor configured to receive the first control signal so as to close when the first control signal is high;

a second nMOS transistor coupled between the common node and the output terminal of the first mixer, the second nMOS transistor configured to receive the first control signal so as to close when the first control signal is high, wherein the input terminal of the first mixer is connected to the output terminal of the first mixer through the first and second nMOS transistors when the first control signal is high; and

a first shunt nMOS transistor coupled between the common node and a voltage source of the first mixer, the shunt nMOS transistor configured to receive the first complement control signal so as to close when the first complement control signal is high;

a second mixer configured to receive at its control terminals the second control signal and the second complement control signal;

a third mixer configured to receive at its control terminals the third control signal and the third complement control signal; and

a fourth mixer configured to receive at its control terminals the fourth control signal and the fourth complement control signal;

a first operation amplifier having input terminals coupled to the output terminals of the first and second mixers; and

a first low pass filter having an input terminal coupled to the output terminal of the first operational amplifier and configured to output a first baseband signal,

a second operation amplifier having input terminals coupled to the output terminals of the third and fourth mixers; and

a second low pass filter having an input terminal coupled to the output terminal of the second operational amplifier and configured to output a second baseband signal.