Modulating CPU frequency and voltage in a multi-core CPU architecture

• US 6,711,447 B1
• Filed: 01/22/2003
• Issued: 03/23/2004
• Est. Priority Date: 01/22/2003
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: Intel Corporation
• Inventors: Saeed, Ali
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Lee, Douglas S.
• Application Number:
  US10/349,537
• Time in Patent Office: 426 Days
• Field of Search: 713/300, 713/320, 713/321, 713/340, 713/322, 713/323, 713/324, 700/82
• US Class Current: 700/82
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method to save power in a computer system is described. A mechanism is used to control the frequency and voltage of a central processing unit (CPU) of a multi-core CPU architecture environment based on the measured levels of multi-threadedness. By controlling the frequency and voltage of the CPU, the battery life of the computer system may be extended.

Claims

1. A computer system, comprising:

a first central processing unit (CPU) core;

a second CPU core coupled to the first CPU core; and

a circuit coupled to the first and the second CPU cores, wherein the circuit deactivates the first CPU core if a measured workload of the cores is less than a first defined level of multi-threadedness.

2. The computer system of claim 1, wherein the first CPU core, the second CPU core, and the circuit are powered by a battery.

3. The computer system of claim 2, wherein the workload is approximately equal to a number of multiple threads spawned divided by a number of total threads.

4. The computer system of claim 1, wherein the first CPU core has a voltage and an operating frequency, wherein the operating frequency of the first CPU core is decreased if the workload is less than a second defined level of multi-threadedness.

5. The computer system of claim 1, wherein the workload is determined by an operating system.

6. An apparatus, comprising:

means for determining workload as a function of a number of multi-threads in a central processing unit (CPU) architecture having a plurality of CPU cores; and

means for reducing an operating frequency of a first CPU core if the level of multi-threads is less than a defined threshold.

7. The apparatus of claim 6, further comprising:

means for reducing a voltage of the first CPU core if the level of multi-threads is less than the defined threshold.

8. The apparatus of claim 6, further comprising:

means for deactivating the first CPU core if the level of multi-threads is less than the defined threshold.

9. The apparatus of claim 6, further comprising:

means for setting the plurality of CPU cores at a lowest needed frequency.

10. A method, comprising:

setting an upper threshold limit;

setting a lower threshold limit;

measuring a workload of a computer based on a number of multi-threaded threads running on the computer; and

decreasing an operating frequency of a first central processing unit (CPU) core if the measured workload is less than the lower threshold limit.

11. The method of claim 10, further comprising:

deactivating the first CPU core; and

keeping a second CPU core active.

12. The method of claim 11, further comprising:

keeping the first CPU core and the second CPU core active if the measured workload is greater than the upper threshold limit.

13. A method, comprising:

defining a threshold level;

determining a workload of a computer system having at least two central processing unit (CPU) cores, wherein the workload is computed by an operating system; and

deactivating a first CPU core if the workload is less than the threshold level.

14. The method of claim 13, wherein the computer system is a battery powered laptop computer system.

15. The method of claim 13, wherein the operating system tracks the workload using a counter, wherein the counter is incremented if a multi-threaded thread is detected, wherein the counter is decremented if a single-threaded thread is detected.

16. An article comprising a machine readable medium having a plurality of machine readable instructions, wherein when the instructions are executed by a processor, the instructions cause a system to:

determine a workload of the system;

send instructions to a plurality of central processing unit (CPU) cores; and

turn off at least one of the plurality of CPU cores if the workload is less than a threshold value.

17. The article of claim 16, further comprising:

reduce a frequency of at least one of the plurality of CPU cores if the workload is less than the threshold value.

18. The article of claim 16, further comprising:

reduce a voltage of at least one of the plurality of CPU cores if the workload is less than the threshold value.

19. The article of claim 16, further comprising:

operate the plurality of CPU cores at a maximum frequency if the system is set to a maximum frequency mode.

20. A system, comprising:

a first processor core having a first operating frequency;

a second processor core having a second operating frequency; and

a circuit coupled to the first and the second processor cores, wherein the circuit decreases the first operating frequency if a measured workload of the system is greater than a defined threshold, wherein the workload is based on the number of multi-threads running on the system.

21. The system of claim 20, wherein the circuit sets the first and the second processor cores to a minimum frequency if the system is placed in a maximum battery mode.

22. The, system of claim 20, wherein the circuit modulates the CPU cores between predetermined frequencies if the system is placed in an auto mode, wherein the set frequencies are a function of the measured workload.

23. The system of claim 22, wherein the predetermined frequencies are stored in basic input/output system.

24. The system of claim 22, wherein the predetermined frequencies are stored in microcode.

25. The system of claim 20, wherein the circuit decreases a voltage of the first circuit if the workload of the system is greater than a defined threshold.