Operating system-independent method and system of determining CPU utilization

• US 6,711,526 B2
• Filed: 12/29/2000
• Issued: 03/23/2004
• Est. Priority Date: 12/29/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cooper, Barnes
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): TSAI, CAROL S W
• Application Number:
  US09/750,676
• Publication Number:
  US 20020087291A1
• Time in Patent Office: 1,180 Days
• Field of Search: 712/89, 712/176, 712/178, 712/182-187, 702/FOR-103, 702/FOR-134, 702/FOR-154, 702/FOR-170, 713/502, 713/323, 713/320, 713/178, 713/500, 713/300, 714/38, 709/102, 709/105, 709/100, 709/101, 709/103, 709/107
• US Class Current: 702/186
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time

Abstract

The utilization of a central processing unit during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the central processing unit. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval.

Claims

1. A central processing unit comprising:

a processor core; and

a time stamp counter to measure a total number of cycles of a central processing unit clock signal that are applied to said processor core during a sampling time interval,

said processor core determines a utilization of said central processing unit utilizing said total number of cycles of said central processing unit clock signal, said processor core calculates a time quantum within said sampling time interval during which said central processing unit clock signal is active within said processor core utilizing said total number of cycles of said central processing unit clock signal and a period of said central processing unit clock signal.

2. The central processing unit as set forth in claim 1, wherein said processor core to determine a utilization of said central processing unit utilizing said total number of cycles of said central processing unit clock signal comprises:

a processor core to calculate a ratio of said time quantum to said sampling time interval.

3. A data processing system comprising:

an independent timer to define a sampling time interval;

a clock generator circuit to generate a system clock signal;

a phase lock loop to receive said system clock signal and to generate a central processing unit clock signal utilizing said system clock signal; and

a central processing unit comprising;

a processor core; and

a time stamp counter to measure a total number of cycles of said central processing unit clock signal that are applied to said processor core during said sampling time interval, wherein said processor core determines a utilization of said central processing unit utilizing said total number of cycles of said central processing unit clock signal, said processor core calculates a time quantum within said sampling time interval during which said central processing unit clock signal is active within said processor core utilizing said total number of cycles of said central processing unit clock signal and a period of said central processing unit clock signal.

4. The data processing system as set forth in claim 3, wherein said processor core to determine a utilization of said central processing unit utilizing said total number of cycles of said central processing unit clock signal comprises:

a processor core to calculate a ratio of said time quantum to said sampling time interval.