Method and apparatus for interrupt redirection for arm processors
First Claim
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1. An interrupt redirection apparatus for inter-processor communication, comprising:
- a plurality of ARM processors;
an interrupt redirection unit for inter-processor communication between a transmission processor and a reception processor, comprising;
an interrupt command register for designating targets and kinds of each interrupt to perform a function for receiving an inter-processor communication request command from a transmission processor and activating an interrupt request signal connected to a reception processor such that the transmission processor sends an inter-processor communication request interrupt to the reception processor, an interrupt data register for designating a start address of a fixed size of message, an interrupt signal generation unit for reading contents in the interrupt command register and activating an FIQ interrupt request signal connected to an ARM processor, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register;
wherein the inter-processor communication between an ARM processor designated as a transmission processor and an ARM processor designated as a reception processor using the interrupt redirection unit comprising;
the message transmitting of the transmission processor comprising;
the transmission processor preparing a transmission message of a fixed size in a region of a preset shared memory, the transmission processor preparing contents of the interrupt command register to be sent to the interrupt redirection unit in order to request an inter-processor communication, the transmission processor preparing a message start address for the interrupt data register, the transmission processor checking the pend field of the interrupt command register of the interrupt redirection unit, the transmission processor performing a write operation to the interrupt command register so as to request the inter-processor communication if the pend field is “
0”
checked as idle, the transmission processor performing a write operation to the interrupt data register so as to transfer the message start address, the transmission processor confirming whether or not the reception processor has received the message by periodically checking the pend field of the interrupt command register, and the transmission processor completing the message transmission if its is confirmed that the reception processor has received the message;
the reception operation processing step comprising the steps of;
the reception processor receiving an FIQ interrupt from the interrupt redirection unit, the reception processor jumping to an FIQ service routine, the reception processor reading the interrupt command register, the reception processor reading the interrupt data registers;
the reception processor checking the class field in the interrupt command register to determine whether a corresponding interrupt is generated interrupt redirection or inter-processor communication, the reception processor branching to an inter-processor communication process routine if it is determined that the interrupt is generated by the inter-processor communication request according to the determined results, the reception processor receiving a message using the message start address transferred through the interrupt data register;
the reception processor clearing the pend field of the interrupt command register to “
0”
so as to inform the transmission processor of the reception of the message, and the reception processor exiting the interrupt service routine.
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Abstract
Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.
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2 Claims
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1. An interrupt redirection apparatus for inter-processor communication, comprising:
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a plurality of ARM processors;
an interrupt redirection unit for inter-processor communication between a transmission processor and a reception processor, comprising;
an interrupt command register for designating targets and kinds of each interrupt to perform a function for receiving an inter-processor communication request command from a transmission processor and activating an interrupt request signal connected to a reception processor such that the transmission processor sends an inter-processor communication request interrupt to the reception processor, an interrupt data register for designating a start address of a fixed size of message, an interrupt signal generation unit for reading contents in the interrupt command register and activating an FIQ interrupt request signal connected to an ARM processor, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register;
wherein the inter-processor communication between an ARM processor designated as a transmission processor and an ARM processor designated as a reception processor using the interrupt redirection unit comprising;
the message transmitting of the transmission processor comprising;
the transmission processor preparing a transmission message of a fixed size in a region of a preset shared memory, the transmission processor preparing contents of the interrupt command register to be sent to the interrupt redirection unit in order to request an inter-processor communication, the transmission processor preparing a message start address for the interrupt data register, the transmission processor checking the pend field of the interrupt command register of the interrupt redirection unit, the transmission processor performing a write operation to the interrupt command register so as to request the inter-processor communication if the pend field is “
0”
checked as idle,the transmission processor performing a write operation to the interrupt data register so as to transfer the message start address, the transmission processor confirming whether or not the reception processor has received the message by periodically checking the pend field of the interrupt command register, and the transmission processor completing the message transmission if its is confirmed that the reception processor has received the message;
the reception operation processing step comprising the steps of;
the reception processor receiving an FIQ interrupt from the interrupt redirection unit, the reception processor jumping to an FIQ service routine, the reception processor reading the interrupt command register, the reception processor reading the interrupt data registers;
the reception processor checking the class field in the interrupt command register to determine whether a corresponding interrupt is generated interrupt redirection or inter-processor communication, the reception processor branching to an inter-processor communication process routine if it is determined that the interrupt is generated by the inter-processor communication request according to the determined results, the reception processor receiving a message using the message start address transferred through the interrupt data register;
the reception processor clearing the pend field of the interrupt command register to “
0”
so as to inform the transmission processor of the reception of the message, and the reception processor exiting the interrupt service routine.
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2. An interrupt redirection apparatus for inter-processor communication, comprising:
-
a plurality of ARM processors;
an interrupt redirection unit for inter-processor communication between a transmission processor and a reception processor, comprising;
an interrupt command register for designating targets and kinds of each interrupt to perform a function for receiving an inter-processor communication request command from a transmission processor and activating an interrupt request signal connected to a reception processor such that the transmission processor sends an inter-processor communication request interrupt to the reception processor, an interrupt data register for designating a start address of a fixed size of message, an interrupt signal generation unit for reading contents in the interrupt command register and activating an FIQ interrupt request signal connected to an ARM processor, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register;
wherein the interrupt command register comprises;
a DID field used for designating a target processor for an interrupt redirection or an interrupt request, and comprised of lower four bits;
a non-use field;
a class field used for discriminating whether a corresponding interrupt is generated by an interrupt redirection request or an inter-processor communication request; and
a pend field is set to “
1”
by a processor requesting the interrupt and cleared to “
0”
by a processor receiving the interrupt in order to represent whether the corresponding interrupt is in processing;
wherein the inter-processor communication between an ARM processor designated as a transmission processor and an ARM processor designated as a reception processor using the interrupt redirection unit comprising;
the message transmitting of the transmission processor comprising;
the transmission processor preparing a transmission message of a fixed size in a region of a preset shared memory, the transmission processor preparing contents of the interrupt command register to be sent to the interrupt redirection unit in order to request an inter-processor communication, the transmission processor preparing a message start address for the interrupt data register, the transmission processor checking the pend field of the interrupt command register of the interrupt redirection unit, the transmission processor performing a write operation to the interrupt command register so as to request the inter-processor communication if the pend field is “
0” and
checked as idle,the transmission processor performing a write operation to the interrupt data register so as to transfer the message start address, the transmission processor confirming whether or not the reception processor has received the message by periodically checking the pend field of the interrupt command register, and the transmission processor completing the message transmission if its is confirmed that the reception processor has received the message;
the reception operation processing step comprising the steps of;
the reception processor receiving an FIQ interrupt from the interrupt redirection unit, the reception processor jumping to an FIQ service routine, the reception processor reading the interrupt command register, the reception processor reading the interrupt data register;
the reception processor checking the class field in the interrupt command register to determine whether a corresponding interrupt is generated by interrupt redirection or inter-processor communication, the reception processor branching to an inter-processor communication process routine if it is determined that the interrupt is generated by the inter-processor communication request according to the determined results, the reception processor receiving a message using the message start address transferred through the interrupt data register, the reception processor clearing the pend field of the interrupt command register to “
0”
so as to inform the transmission processor of the reception of the message, and the reception processor exiting the interrupt service routine.
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Specification
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Current AssigneeElectronics and Telecommunications Research Institute
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Original AssigneeElectronics and Telecommunications Research Institute
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InventorsPark, Kyoung, Kim, Yong Youn, Moh, Sang Man
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Primary Examiner(s)Auve, Glenn A.
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Assistant Examiner(s)Lee, Christopher E.
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Application NumberUS10/028,702Publication NumberTime in Patent Office816 DaysField of Search710/260, 710/266, 710/268, 710/261, 710/264, 703/25, 709/102US Class Current710/260CPC Class CodesG06F 13/24 using interrupt G06F13/32 t...
