Data processing unit including central unit and peripheral unit driven by separate power supplies

• US 6,711,692 B1
• Filed: 05/26/2000
• Issued: 03/23/2004
• Est. Priority Date: 01/04/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hata, Masayuki, Maeda, Hiromi, Shimazu, Yukihiko
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Trujillo, James K.
• Application Number:
  US09/580,209
• Time in Patent Office: 1,397 Days
• Field of Search: 713/310, 713/320, 713/340, 713/322, 713/300, 714/15, 714/17, 714/18, 714/19, 714/48
• US Class Current: 713/324
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A data processing unit includes a first power supply consisting of a stable power supply, a central unit operating on the firsts power supply, a second power supply, a peripheral unit operating on the second power supply, an interface block for transferring an external signal to the peripheral unit, and a power-down detector operating on the first power supply and connected to the second power supply, for detecting a power down of the second power supply and for generating a signal informing of the power down when it occurs. This power down signal can prevent supply of the external input signal to the central unit. The data processing unit solves problems of conventional data processing units including separate central unit and peripheral power supplies in that an unexpected power down of the peripheral use power supply can cause malfunctions of the central unit because of, e.g., an undesired interrupt signal.

Claims

1. A data processing unit comprising:

a first power supply consisting of a stable power supply;

a central unit operating on said first power supply;

a second power supply;

a peripheral unit operating on said second power supply;

an interface block for transferring an external input signal to said peripheral unit; and

a power-down detector operating on said first power supply and directly connected to said second power supply, for detecting a power down of said second power supply and for generating a signal informing of the power down when it takes place, wherein said central unit enters a reduced power consumption mode upon receiving said power down signal.

2. The data processing unit according to claim 1, wherein said central unit comprises a processing block for processing the external input signal supplied through said peripheral unit, and wherein said processing block disables the external input signal in response to the signal informing of the power down output from said power-down detector.

3. The data processing unit according to claim 1, wherein said central unit comprises an interrupt handling circuit for executing interrupt processing of the external input signal consisting of an external interrupt signal supplied through said peripheral unit, and wherein the interrupt handling circuit disables the external interrupt signal in response to the signal informing of said power down output from said power-down detector.

4. The data processing unit according to claim 1, wherein said central unit comprises a processing block for temporarily storing and holding a data value of the external input signal supplied through said peripheral unit, and wherein said processing block holds the data value temporarily stored, and disables further input of the external input signal to said processing block in response to the signal informing of the power down output from said power-down detector.

5. The data processing unit according to claim 1, wherein said central unit comprises a CPU for executing operations, and wherein said CPU executes an interrupt handler that disables an input of the external input signal in response to the signal informing of the power down from said power-down detector.

6. The data processing unit according to claim 1, wherein said central unit includes said power-down detector.

7. A data processing unit comprising:

a first power supply consisting of a stable power supply;

a central unit operating on said first power supply;

a second power supply;

a peripheral unit operating on said second power supply;

an interface block for transferring an external input signal to said peripheral unit; and

a power-down detector operating on said first power supply and connected to said second power supply, for detecting a power down of said second power supply by comparing a voltage level of said second power supply to a reference voltage and for outputting a signal informing said central unit of the power down when it occurs, wherein said central unit operates in a reduced power mode upon receiving said power down signal.

8. The data processing unit according to claim 7, wherein said central unit comprises a processing block for processing the external input signal supplied through said peripheral unit, and wherein said processing block disables the external input signal in response to the signal informing of the power down output from said power-down detector.

9. The data processing unit according to claim 7, wherein said central unit comprises an interrupt handling circuit for executing interrupt processing of the external input signal consisting of an external interrupt signal supplied through said peripheral unit, and wherein said interrupt handling circuit disables the external interrupt signal in response to the signal informing of the power down output from said power-down detector.

10. The data processing unit according to claim 7, wherein said central unit comprises a processing block for temporarily storing and holding a data value of the external input signal supplied through said peripheral unit, and wherein said processing block holds the data value temporarily stored, and disables further input of the external input signal to said processing block in response to the signal informing of the power down output from said power-down detector.

11. The data processing unit according to claim 7, wherein said central unit comprises a CPU for executing operations, and wherein said CPU executes an interrupt handler that disables an input of the external input signal in response to the signal informing of the power down from said power-down detector.

12. The data processing unit according to claim 7, wherein said central unit includes said power-down detector.