Write and erase protection in a synchronous memory

• US 6,711,701 B1
• Filed: 08/25/2000
• Issued: 03/23/2004
• Est. Priority Date: 08/25/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F., Abedifard, Ebrahim
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Manoskey, Joseph D
• Application Number:
  US09/648,508
• Time in Patent Office: 1,306 Days
• Field of Search: 714/24, 714/22, 714/721, 714/14, 714/42, 711/103
• US Class Current: 714/24
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges

Abstract

A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.

Claims

1. A memory device comprising:

a memory array;

programmable, volatile register to store protection data;

a voltage detector to determine if a memory power supply voltage drops below a predetermined level;

control circuitry to program the protection data in response to the voltage detector and read the programmable volatile register and prevent erase or write operations to the memory array in response to the read protection data; and

a non-volatile register;

coupled to the volatile register for storing default protection data.

2. The memory of claim 1 wherein the memory array is arranged in a plurality of addressable blocks and the programmable register circuitry has a plurality of data bits, each of the plurality of data bits corresponds to one of the plurality of addressable blocks.

3. The memory of claim 2 wherein the memory array has 16 addressable blocks and the programmable register circuitry has 16 corresponding data bits.

4. The memory of claim 1 wherein the memory array comprises non-volatile memory cells.

5. A synchronous memory comprising:

a memory array arranged in addressable blocks;

a multi-bit, volatile register to store protection data, wherein each one of the multi-bits corresponds to one of the addressable blocks of the memory array;

a voltage detector to determine if a memory power supply voltage drops below a predetermined level;

control circuitry to program the volatile register and prevent erase or write operations to the memory array in response to the protection data; and

a non-volatile register coupled to the volatile register, wherein the non-volatile register stores default protection data.

6. The memory of claim 5 wherein the memory array has 16 addressable blocks and the programmable register circuitry has 16 corresponding data bits.

7. A memory system comprising:

a memory controller; and

a memory coupled to the memory controller and comprising,

a memory array,

a programmable volatile register circuitry to store protection data,

a non-volatile register, coupled to the volatile register, that stores default protection data,

a voltage detector to determine if a memory power supply voltage drops below a predetermined level, and

control circuitry to program protection data into the volatile register circuitry, in response to the memory power supply voltage, and prevent erase or write operations to the memory array in response to the protection data.

8. The memory system of claim 7 wherein the memory further comprises a status register and the memory controller can read data from the status register.

9. The memory system of claim 8 wherein the status register data indicates a protect status of the memory.

10. A method of operating a memory device comprising:

loading default protection data from a non-volatile register to a volatile register;

monitoring a power supply voltage coupled to the memory device;

setting a content of the volatile register to a protection status when the supply voltage drops below a predetermined value;

receiving a write or erase operation command;

reading the contents of the volatile register with an internal control circuit in response to the write or erase command; and

prohibiting the write or erase operation in response to the status of the volatile register.

11. The method of claim 10 further comprises providing an error signal on external connections in response to the status of the register.

12. The method of claim 11 further comprises reading the status of the register with an external memory controller in response to the error signal.

13. The method of claim 10 further comprising:

performing a reset operation on the memory device after the supply voltage drops below the predetermined value; and

allowing subsequent write or erase operations to be performed after the reset operation is performed.

14. A method of operating a memory device comprising:

loading default protection data from a non-volatile protection register to a volatile protection register;

monitoring a power supply voltage coupled to the memory device with an internal voltage detector;

setting a content of the volatile protection register to a protect status when the supply voltage drops below a predetermined value;

receiving a write or erase operation command from an external memory controller;

reading the contents of the volatile protection register with an internal control circuit in response to the write or erase command;

prohibiting the write or erase operation in response to the status of the volatile protection register; and

providing an error signal to the external memory controller in response to the prohibited write or erase operation.

15. A method of protecting a memory comprising:

loading a volatile protection register with default protection data from a non-volatile protection register;

setting the volatile protection register to a first state to allow write or erase operations to memory cells of the memory;

monitoring a power supply voltage coupled to the memory device; and

setting the volatile protection register to a second state to prohibit the write or erase operations when the supply voltage drops below a predetermined value.