Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method

• US 6,711,705 B1
• Filed: 07/21/2000
• Issued: 03/23/2004
• Est. Priority Date: 07/21/1999
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Yasui, Takahiro
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US09/621,326
• Time in Patent Office: 1,341 Days
• Field of Search: 714/723, 714/42, 714/724, 714/727, 714/710, 365/222, 365/201, 324/760, 710/260, 710/10, 710/5, 345/519, 712/245
• US Class Current: 714/723
• CPC Class Codes: G11C 2029/5604 Display of error information
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A method and apparatus for analyzing repair of failure cells in a memory are capable of detecting an address of a failure memory cell in a short time. The memory testing apparatus includes a failure relief analyzer for testing a memory having a plurality of storage areas, counting the number of failure memory cells for each storage area, and reading out the counted number of failure memory cells. The apparatus has an analyzed storage area detector for searching whether a failure memory cell exists and determining whether a failure relief analysis should be performed, a failure line searching apparatus for searching row addresses to detect whether a failure memory cell exists, and an address scanning apparatus whose operation is started when the failure line searching apparatus detects the presence of a failure memory cell, and for detecting a column address in the direction orthogonal to the row address line on which the detected failure memory cell exists.

Claims

1. A method of analyzing a repair of failure cell in a memory comprising the steps of:

testing a memory having a plurality of storage areas and a plurality of spare lines for relieving failures in said storage areas, and storing in a failure memory cell storage an indication of failure memory cells in the storage areas;

counting for each of the storage areas a number of failure memory cells for each row address, a number of failure memory cells for each column address, and a total number of failure memory cells by accessing each memory cell of the failure memory cell storage once;

storing the counted numbers as stored data;

detecting a must-repair;

updating, after a must-repair has been detected, the stored data and the number of spare lines available for relieving a failure to ones after the detected must-repair has been repaired to show said must-repair has been repaired;

searching the updated stored data to determine whether any failure memory cell is present or not for each row address or each column address of each of the storage areas;

temporarily stopping, each time a failure memory cell is detected, the searching of failure memory cells for each row address or each column address and searching a column address or row address of the detected failure memory cell;

temporarily stopping, when a column address or row address of the failure memory cell is detected, the searching of a column address or row address of the detected failure memory cell and storing the address of the storage area at which the detected failure memory cell exists, the row address and the column address of the detected failure memory cell;

resuming, after the address of the storage area at which the detected failure memory cell exists, the row address and the column address of the detected failure memory cell have been stored, the searching of a column address or row address; and

resuming, when the searching of a column address or row address has been ended, the searching of failure memory cells for each row address or each column address.

2. A memory testing apparatus for testing a memory having a plurality of storage areas and a plurality of spare lines for relieving failures in said storage areas, and storing in a failure memory cell storage of a failure relief analyzer an indication of failure memory cells in the storage areas, said failure relief analyzer comprising:

means for counting, for each of the storage areas, a number of failure memory cells for each row address, a number of failure memory cells for each column address, and a total number of failure memory cells by accessing each memory cell of the failure memory cell storage once;

a failure memory cell number storage that stores the counted numbers as stored data;

a spare line number memory for storing a number of spare lines available for repair, said spare line number memory storing for each storage area a number of spare lines provided in row address direction and a number of spare lines provided in column address direction;

data updating apparatus for carrying out, each time a must-repair is detected, a process of updating the stored data and the number of spare lines to ones after the must-repair has been detected to show said must-repair has been repaired;

an analyzed storage area detector for searching the updated stored data whether a failure memory cell exists or not in each storage area and for determining whether a respective storage area is a storage area for which a failure relief analysis should be performed;

a failure line searching apparatus for searching, in the storage area where said analyzed storage area detector has determined that a failure relief analysis should be performed, whether a failure memory cell exists or not in each row address or column address;

an address scanning apparatus started when said failure line searching apparatus detects a row address or column address where a failure memory cell exists, and for detecting a column address or row address of the detected failure memory cell;

a failure cell address memory for storing the address of the failure memory cell detected by said failure line searching apparatus and said address scanning apparatus and the address of the storage area at which the detected failure memory cell exists; and

a controller for controlling to temporarily stop, when the failure line searching apparatus has detected a row address or column address where a failure memory cell exists, the address searching for the failure memory cell by the failure line searching apparatus and to operate the address scanning apparatus;

to temporarily stop, when the address scanning apparatus has detected a column address or row address of the detected failure memory cell, the column address or row address searching by the address scanning apparatus;

to store in the failure cell address memory the address of the failure memory cell detected by the failure line searching apparatus and the address scanning apparatus and the address of the storage area at which the detected failure memory cell exists;

to resume, after the row address and the column address of the failure memory cell and the address of the storage area at which the failure memory cell exists have been stored, the column address or row address searching by the address scanning apparatus; and

to resume, when the column address or row address searching has been ended, the address searching for the failure memory cell by the failure line searching apparatus.

3. The memory testing apparatus as set forth in claim 2, wherein said analyzed storage area detector of said failure relief analyzer comprises:

a storage area address generator for generating addresses given respectively to said plurality of storage areas constituting the memory under test;

a total failure number counter/memory accessed by storage area address signals outputted from said storage area address generator and for storing the total number of failure memory cells for each storage area;

zero detector for detecting the fact that the total number of failure memory cells read out of said total failure number counter/memory is “

0”

or a numerical value other than “

0”

.

4. The memory testing apparatus as set forth in claim 2, wherein said failure line searching apparatus of said failure relief analyzer comprises:

a row address generator or column address generator for generating row addresses or column addresses on each of the storage areas;

a row address failure number counter/memory or column address failure number counter/memory for storing the number of failure memory cells on each row address line or each column address line for each storage area;

zero detector for detecting whether the number of failure memory cells read out of either one of said row address failure number counter/memory or column address failure number counter/memory is “

0”

or a numerical value other than “

0”

; and

means of starting the operation of said address scanning apparatus each time said zero detector detects a numerical value other than “

0”

.

5. The memory testing apparatus as set forth in claim 2, wherein said address scanning apparatus of said failure relief analyzer comprises:

a column address generator or row address generator for generating column addresses or row addresses on each of the storage areas;

a column address failure number counter/memory or row address failure number counter/memory for storing the number of failure memory cells on each column address line or each row address line for each storage area;

zero detector for detecting whether the number of failure memory cells read out of either one of said column address failure number counter/memory or row address failure number counter/memory is “

0”

or a numerical value other than “

0”

; and

writing control means for causing addresses to be stored in said failure cell address memory, said addresses being specified by address signals generated respectively from said storage area address generator, said row address generator and said column address generator, each time said zero detector detects a numerical value other than “

0” and

at the same time a read-out data of a failure analysis memory provided in the memory testing apparatus is “

fail”

.