Stress controlled dielectric integrated circuit fabrication

• US 6,713,327 B2
• Filed: 02/05/2001
• Issued: 03/30/2004
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): Fahmyl, Wael
• Assistant Examiner(s): Rao, Shrinivas H
• Application Number:
  US09/775,670
• Publication Number:
  US 20020014673A1
• Time in Patent Office: 1,149 Days
• Field of Search: 438/157, 438/149, 438/283, 438/151, 257/347, 257/329, 257/508, 257/663
• US Class Current: 438/151
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices, wherein said insulating membrane has a surface stress level of less than 8×

10⁸ dynes/cm²; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer.

2. The method of claim 1, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

3. The method of claim 1, further comprising the step of forming a trench in the substrate isolating at least one of the semiconductor devices from the others.

4. The method of claim 1, wherein the baffler layer is formed lying less than 50 μ

m below the principal surface.

5. The method of claim 1, further comprising the step of forming conductors in the insulating membrane for interconnecting the semiconductor devices.

6. The method of claim 1, wherein the step of removing comprises the step of leaving an edge portion of the substrate unaffected, thereby supporting a central portion of the substrate.

7. The method of claim 1, further comprising the step of attaching an annular support ring to an edge portion of the substrate.

8. The method of claim 1, wherein the step of depositing includes the step of supplying SiH₄ gas, N₂O gas, and N₂ gas at a temperature of about 400°

C.

9. The method of claim 1, wherein the step of depositing includes the step of supplying SiH₄ gas, NH₃ gas, and N₂ gas at a temperature of about 400°

C.

10. The method of claim 1, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

11. The method of claim 1, wherein the step of forming a barrier layer comprises the step of epitaxially growing on a surface of the substrate a layer including boron.

12. The method of claim 1, further comprising the steps of:

forming an additional thickness of stress-controlled insulating material over the membrane; and

forming a plurality of recesses in the additional thickness.

13. The method of claim 1, wherein the step of forming semiconductor devices separates the semiconductor devices such that, after the step of removing, each semiconductor device is electrically isolated by the insulating membrane from each of the other semiconductor devices.

14. The method of claim 1, wherein the step of forming semiconductor devices separates the semiconductor devices from the substrate such that each semiconductor devices is electrically isolated from the substrate by the insulating membrane.

15. The method of claim 1, wherein the membrane is selected from the group consisting of silicon dioxide and silicon nitride.

16. The method of claim 1, wherein the insulating membrane has a thickness in the range of about 2 to about 15 micrometers.

17. The method of claim 1, further comprising the step of etching a recess in a back surface of the substrate.

18. The method of claim 1, wherein the insulating membrane is foamed of silicon dioxide.

19. The method of claim 1, wherein the insulating membrane is formed of silicon nitride.

20. The method of claim 1, wherein the step of forming a barrier layer comprises epitaxial processing.

21. The method of claim 20, wherein the step of epitaxial processing comprises:

forming a heavily doped boron layer; and

epitaxially growing a SiGe layer of less than 25% Ge on either side of the boron layer.

22. The method of claim 1, wherein the substrate comprises polycrystalline silicon.

23. The method of claim 1, wherein the substrate comprises an amorphous material.

24. The method of claim 6, wherein a width of the edge portion is less than about 1 cm.

25. The method of claim 7, wherein the support ring has a thickness in the range of about 25 to about 100 mils.

26. The method of claim 8, wherein the step of depositing is performed at a pressure of about 1.8 torr.

27. The method of claim 9, wherein the step of depositing is performed at a pressure of about 2.3 torr.

28. The method of claim 8, wherein the step of depositing includes applying both high and low radio frequency power.

29. The method of claim 9, wherein the step of depositing includes applying both high and low radio frequency power.

30. The method of claim 1, wherein the barrier layer is formed with a material selected from the group consisting of boron, oxygen, nitrogen, and porous silicon.

31. The method of claim 12, wherein a depth of the recesses is about 75% of the additional thickness.

32. The method of claim 31, wherein a width of the recesses is about two to three times the depth of the recesses.

71. The method of claim 1, wherein the substrate has an area greater than 1 square cm.

72. The method of claim 5, wherein the conductors are formed in the membrane both above and below the semiconductor devices.

73. The method of claim 1, further comprising at least one additional processing step performed at a temperature in excess of 400°

C.

74. The method of claim 73, wherein said additional processing step comprises implant activation annealing.

80. The method of claim 1, wherein said stress is tensile.

82. The method of claim 1, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

143. The method of claim 1, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

144. The method of claim 143, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

145. The method of claim 143, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

146. The method of claim 145, wherein said stress is tensile.

33. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices;

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer; and

attaching an annular support ring to an edge portion of the substrate.

34. The method of claim 33, wherein the support ring has a thickness in the range of about 25 to about 100 mils. the probe points are spaced apart by less than about 2 μ

m.

83. The method of claim 33, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

84. The method of claim 33, wherein the substrate comprises polycrystalline silicon.

85. The method of claim 33, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

86. The method of claim 33, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

87. The method of claim 86, wherein said stress is tensile.

147. The method of claim 33, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

148. The method of claim 147, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

149. The method of claim 147, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

150. The method of claim 149, wherein said stress is tensile.

191. The method of claim 33, comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

35. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface by forming a heavily doped boron layer and epitaxially growing a SiGe layer of less then 25% Ge on either side of the boron layer;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer.

88. The method of claim 35, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

89. The method of claim 35, wherein the substrate comprises polycrystalline silicon.

90. The method of claim 35, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

91. The method of claim 35, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

92. The method of claim 91, wherein said stress is tensile.

151. The method of claim 35, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

152. The method of claim 151, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

153. The method of claim 151, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

154. The method of claim 153, wherein said stress is tensile.

192. The method of claim 35, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

36. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface, wherein the substrate comprises polycrystalline silicon;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices;

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer.

93. The method of claim 36, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

94. The method of claim 36, wherein the substrate comprises polycrystalline silicon.

95. method of claim 36, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

96. The method of claim 36, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

97. The method of claim 96, wherein said stress is tensile.

155. The method of claim 36, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

156. The method of claim 155, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

157. The method of claim 155, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

158. The method of claim 157, wherein said stress is tensile.

193. The method of claim 36, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

37. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface, wherein the substrate comprises an amorphous material;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer.

98. The method of claim 37, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

99. The method of claim 37, wherein the substrate comprises polycrystalline silicon.

100. The method of claim 37, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

101. The method of claim 37, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

102. The method of claim 101 wherein said stress is tensile.

159. The method of claim 37, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

160. The method of claim 159, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

161. The method of claim 159, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

162. The method of claim 161, wherein said stress is tensile.

194. The method of claim 37, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

38. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices;

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer;

forming an additional thickness of stress-controlled insulating material over the membrane; and

forming a plurality of recesses in the additional thickness, wherein a depth of the recesses is about 75% of the additional thickness and wherein a width of the recesses is about two to three times the depth of the recesses.

103. The method of claim 38, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

104. The method of claim 38, wherein the substrate comprises polycrystalline silicon.

105. The method of claim 38, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

106. The method of claim 38, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

107. The method of claim 106, wherein said stress is tensile.

163. The method of claim 38, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

164. The method of claim 163, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

165. The method of claim 163, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

166. The method of claim 165, wherein said stress is tensile.

195. The method of claim 38, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

39. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices, wherein said insulating membrane is deposited with a material selected from the group consisting of silicon dioxide and silicon nitride and has a surface stress level of less than 8×

10⁸ dynes/cm² ; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer.

40. The method of claim 39, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

41. The method of claim 39, further comprising the step of forming a trench in the substrate isolating at least one of the semiconductor devices from the others.

42. The method of claim 39, wherein the barrier layer is formed lying less than 50 μ

m below the principal surface.

43. The method of claim 39, further comprising the step of forming conductors in the insulating membrane for interconnecting the semiconductor devices.

44. The method of claim 39, wherein the step of removing comprises the step of leaving an edge portion of the substrate unaffected, thereby supporting a central portion of the substrate.

45. The method of claim 39, further comprising the step of attaching an annular support ring to an edge portion of the substrate.

46. The method of claim 39, wherein the step of depositing includes the step of supplying SiH₄ gas, N₂O gas, and N₂ gas at a temperature of about 400°

C.

47. The method of claim 39, wherein the step of depositing includes the step of supplying SiH₄ gas, NH₃ gas, and N₂ gas at a temperature of about 400°

C.

48. The method of claim 39, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

49. The method of claim 39, wherein the step of forming a barrier layer comprises the step of epitaxially growing on a surface of the substrate a layer including boron.

50. The method of claim 39, further comprising the steps of:

forming an additional thickness of stress-controlled insulating material over the membrane; and

forming a plurality of recesses in the additional thickness.

51. The method of claim 39, wherein the step of forming semiconductor devices separates the semiconductor devices such that, after the step of removing, each semiconductor device is electrically isolated by the insulating membrane from each of the other semiconductor devices.

52. The method of claim 39, wherein the step of forming semiconductor devices separates the semiconductor devices from the substrate such that each semiconductor device is electrically isolated from the substrate by the insulating membrane.

53. The method of claim 39, wherein the membrane is selected from the group consisting of silicon dioxide and silicon nitride.

54. The method of claim 39, wherein the insulating membrane has a thickness in the range of about 2 to about 15 micrometers.

55. The method of claim 39, further comprising the step of etching a recess in a back surface of the substrate.

56. The method of claim 39, wherein the insulating membrane is formed of silicon dioxide.

57. The method of claim 39, the insulating membrane is formed of silicon nitride.

58. The method of claim 39, wherein the step of forming a barrier layer comprises epitaxial processing.

59. The method of claim 58, wherein the step of epitaxial processing comprises:

forming a heavily doped boron layer; and

epitaxially growing a SiGe layer of less than 25% Ge on either side of the boron layer.

60. The method of claim 39, wherein the substrate comprises polycrystalline silicon.

61. The method of claim 39, wherein the substrate comprises an amorphous material.

62. The method of claim 44, wherein a width of the edge portion is less than about 1 cm.

63. The method of claim 45, wherein the support ring has a thickness in the range of about 25 to about 100 mils.

64. The method of claim 46, wherein the step of depositing is performed at a pressure of about 1.8 torr.

65. The method of claim 47, wherein the step of depositing is performed at a pressure of about 2.3 torr.

66. The method of claim 46, wherein the step of depositing includes applying both high and low radio frequency power.

67. The method of claim 47, wherein the step of depositing includes applying both high and low radio frequency power.

68. The method of claim 39, wherein the barrier layer is formed with a material selected from the group consisting of boron, oxygen, nitrogen, and porous silicon.

69. The method of claim 50, wherein a depth of the recesses is about 75% of the additional thickness.

70. The method of claim 69, Wherein a width of the recesses is about two to three times the depth of the recesses.

75. The method of claim 39, wherein the substrate has an area greater than a square cm.

76. The method of claim 43, wherein the conductors are formed in the membrane both above and below the semiconductor devices.

77. The method of claim 39, further comprising at least one additional processing step performed at a temperature in excess of 400°

C.

78. The method of claim 77, wherein said additional processing step comprises implant activation annealing.

81. The method of claim 39, wherein said stress is tensile.

108. The method of claim 39, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

167. The method of claim 39, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

168. The method of claim 167, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

169. The method of claim 167, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

170. The method of claim 169, wherein said stress is tensile.

79. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the device layer;

wherein structural integrity of a substantial portion of the integrated circuit is derived primarily from the stress-controlled insulated membrane.

109. The method of claim 79, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

110. The method of claim 79, wherein the substrate comprises polycrystalline silicon.

111. The method of claim 79, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

112. The method of claim 79, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

113. The method of claim 112, wherein said stress is tensile.

171. The method of claim 79, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

172. The method of claim 171, wherein the stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

173. The method of claim 171, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

174. The method of claim 173, wherein said stress is tensile.

196. The method of claim 79, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

114. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices, wherein a portion of the substrate below the barrier layer and underlying the device layer is removable from a backside of the substrate opposite the principal surface, while retaining structural integrity of the integrated circuit.

115. The method of claim 114, further comprising the step of forming a trench in the substrate isolating at least one of the semiconductor devices from the others.

116. The method of claim 114, further comprising the step of forming conductors in the insulating membrane for interconnecting the semiconductor devices.

117. The method of claim 114, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

118. The method of claim 117, wherein said stress is tensile.

119. The method of claim 114 wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

120. The method of claim 114, wherein the membrane is selected from the group consisting of silicon dioxide and silicon nitride.

121. The method of claim 114, wherein the step of forming a barrier layer comprises epitaxial processing.

122. The method of claim 114, wherein the substrate comprises polycrystalline silicon.

123. The method of claim 114, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

124. The method of claim 114, wherein the barrier layer is formed with a material selected from the group consisting of boron, oxygen, nitrogen, and porous silicon.

175. The method of claim 114, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

176. The method of claim 175, wherein the stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

177. The method of claim 175, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

178. The method of claim 177, wherein said stress is tensile.

197. The method of claim 114, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

125. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface wherein a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices; and

thinning the substrate by removing at least a portion of the substrate from a backside of the substrate opposite the principal surface below the barrier layer and underlying the device layer.

126. The method of claim 125, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

127. The method of claim 125, wherein the substrate comprises polycrystalline silicon.

128. The method of claim 125, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

129. The method of claim 125, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

130. The method of claim 129, wherein said stress is tensile.

179. The method of claim 125, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

180. The method of claim 179, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

181. The method of claim 179, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

182. The method of claim 181, wherein said stress is tensile.

198. The method of claim 125, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

131. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices, wherein a portion of the substrate below the barrier layer and underlying the device layer is removable from a backside of the substrate opposite the principal surface.

132. The method of claim 131, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

133. The method of claim 131, wherein the substrate comprises polycrystalline silicon.

134. The method of claim 131, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

135. The method of claim 131, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

136. The method of claim 135, wherein said stress is tensile.

183. The method of claim 131, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

184. The method of claim 183, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

185. The method of claim 183, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

186. The method of claim 185, wherein said stress is tensile.

199. The method of claim 131, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

137. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming semiconductor devices on the principal surface within a device layer above the barrier layer, a plurality of semiconductor devices overlying the barrier layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices.

138. The method of claim 137, wherein the substrate is made from one of singe crystal semiconductor material and polycrystalline semiconductor material.

139. The method of claim 137, in the substrate comprises polycrystalline silicon.

140. The method of claim 137, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

141. The method of claim 137, wherein the insulating membrane is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

142. The method of claim 141, wherein said stress is tensile.

187. The method of claim 137, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

188. The method of claim 187, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

189. The method of claim 187, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

190. The method of claim 189, wherein said stress is tensile.

200. The method of claim 137, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

201. A method of making an integrated circuit comprising the steps of:

providing a substrate having a principal surface;

forming a barrier layer in the substrate parallel to the principal surface;

forming an epitaxial layer above the barrier layer on the principal surface;

forming semiconductor devices in the epitaxial layer;

after forming the semiconductor devices, depositing a stress-controlled insulating membrane over the semiconductor devices, wherein said insulating membrane has a surface stress level of less than 8×

10⁸ dynes/cm²; and

thinning the substrate by removing from a backside of the substrate opposite the principal surface at least a portion of the substrate below the barrier layer and underlying the epitaxial layer.

202. The method of claim 201, further comprising the steps of:

forming an epitaxial layer on the principal surface; and

forming the semiconductor devices in the epitaxial layer.

203. The method of claim 201, wherein the stress-controlled insulating membrane comprises at least one or more stress-controlled dielectric layers.

204. The method of claim 203, wherein said stress-controlled dielectric layer is selected from the group consisting of silicon dioxide and silicon nitride.

205. The method of claim 203, wherein said stress-controlled dielectric layer is caused to have a stress of about 8×

10⁸ dynes/cm² or less.

206.The method of claim 205, wherein said stress is tensile.

206. The method of claim 201, wherein the step of forming a barrier layer comprises:

implanting the substrate with a material to form the barrier layer, wherein the implanted material is one of oxygen and nitrogen.

207. The method of claim 201, wherein the substrate comprises polycrystalline silicon.

208. The method of claim 201, wherein the substrate is made from one of single crystal semiconductor material and polycrystalline semiconductor material.