Semiconductor processing method

• US 6,713,355 B2
• Filed: 05/08/2003
• Issued: 03/30/2004
• Est. Priority Date: 07/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Korn, David, Gilton, Terry
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/431,822
• Publication Number:
  US 20030203610A1
• Time in Patent Office: 327 Days
• Field of Search: 438/279, 438/301, 438/303, 438/625, 438/261
• US Class Current: 438/279
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover. The stack in at least one cross section defines a channel length within the substrate of less than 1 micron, with the stack comprising conductive material formed over a gate dielectric layer. An insulative layer is formed on outer lateral edges of the conductive material, with such layer having opposing substantially continuous straight linear outer lateral edges over all conductive material of the gate stack within the one cross section.

Claims

1. A semiconductor processing method comprising:

forming a stack of at least first and second conductive layers for an electronic component over a substrate, the first and second conductive layers having different oxidation rates when exposed to a thermal oxidizing atmosphere, the layer with the higher oxidation rate having an outer lateral edge which is recessed laterally inward of a corresponding outer lateral edge of the layer with the lower oxidation rate; and

exposing the stack of conductive layers to the thermal oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers, the oxide layer having a substantially continuous straight linear outer lateral edge portion extending over the first and second conductive layers.

2. The method of claim 1 comprising forming the higher oxidation rate layer over the lower oxidation rate layer.

3. The method of claim 1 comprising forming the lower oxidation rate layer over the higher oxidation rate layer.

4. The method of claim 1 comprising forming another layer over the at least first and second conductive layers, the another layer having a lower oxidation rate than the layer having said higher oxidation rate when exposed to the oxidizing atmosphere, the outer lateral edge of the layer with said higher oxidation rate being recessed inwardly of a corresponding outer lateral edge of the another layer.

5. The method of claim 4 wherein the another layer is electrically insulative.

6. The method of claim 1 wherein one of the at least first and second conductive layers comprises conductively doped polysilicon and another of the at least first and second conductive layers comprises a refractory metal silicide.

7. The method of claim 1 wherein the layer with the higher oxidation rate has an opposing pair of outer lateral edges which are recessed laterally inward of a corresponding pair of opposing outer lateral edge of the layer with the lower oxidation rate, the exposing being effective to grow an oxide layer over each of the outer lateral edges of the pair of outer lateral edges of the first and second layers, each of the oxide layers having a respective substantially continuous straight linear outer lateral edge portion extending over the first and second conductive layers.

8. The method of claim 1 further comprising ion implanting into the substrate proximate the substantially continuous straight linear outer lateral edge of the oxide layer after the exposing.

9. The method of claim 1 further comprising forming an insulative layer over the oxide layer and thereafter anisotropically etching the insulative layer to form an insulative spacer over the oxide layer.

10. The method of claim 1 further comprising fabricating the stack as at least part of a gate of a field effect transistor.

11. The method of claim 1 wherein the outer lateral edges of the first and second conductive layers are each straight linear prior to the exposing.

12. The method of claim 1 wherein the portion extends over substantially all at the outer lateral edges of the first and second conductive layers.