Method for making a semiconductor device comprising a stack alternately consisting of silicon layers and dielectric material layers

• US 6,713,356 B1
• Filed: 04/23/2002
• Issued: 03/30/2004
• Est. Priority Date: 06/28/1999
• Status: Expired due to Fees

• Current Assignee: Orange S.A.
• Original Assignee: Orange S.A.
• Inventors: Skotnicki, Thomas, Jurczak, Malgorzata
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): Luhrs, Michael K.
• Application Number:
  US10/019,169
• Time in Patent Office: 707 Days
• Field of Search: 438/285, 438/157, 438/424, 438/738
• US Class Current: 438/285
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A method of fabricating a semiconductor device consisting of a silicon substrate on which is formed a stack of layers is described. The stack may have successively at least one first and one second combination. Each combination may consist, with reference to the substrate, of a thin bottom SiGe layer and a thin top silicon layer. A thin silicon dioxide film (18) is formed on the thin top silicon layer of the second combination so that the layer concerned supports the layers of the stack on at least two opposite lateral sides of the stack. Successive selective lateral etching of the SiGe layers is then carried out to form tunnels which are filled with a dielectric material.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming on a main surface of a silicon substrate, a stack comprising successively at least one first combination and one second combination, wherein each combination comprises, with reference to the substrate, a thin bottom layer of germanium, or a germanium and silicon alloy (SiGe), and a thin top layer of silicon;

forming on the thin top silicon layer of the second combination, a thin silicon dioxide layer that supports the layers of the stack on at least two opposite lateral sides of the stack;

forming a hard mask on the thin silicon dioxide layer so as to form two separate opposed areas on respective opposite sides of two opposite edges of the hard mask;

etching the thin silicon dioxide layer, the top silicon layer and at least part of the lower germanium or SiGe layer of the second combination in the two separate opposed areas;

selectively laterally etching the bottom germanium or SiGe layer of the second combination to form a tunnel;

thermally oxidizing the tunnel of the second combination;

etching the top silicon layer and at least part of the bottom germanium or SiGe layer of the first combination in the two separate opposed areas; and

selectively laterally etching the bottom germanium or SiGe layer of the first combination to form a tunnel.

2. The method of claim 1, wherein the germanium and silicon SiGe alloy comprises an alloy formed of germanium and silicon such that Si_1-xGe_x (0<

x≦

1) and Si_1-x-yGe_xC_y (0<

x≦

0.95;

0<

y≦

0.05).

3. The method of claim 1, wherein the hard mask comprises a material which can be selectively etched relative to silicon, germanium, and/or SiGe.

4. The method of claim 1, wherein etching of the separate opposed areas comprises plasma etching.

5. The method of claim 1, wherein etching of the germanium or SiGe layers comprises either anisotropic plasma etching, which is selective relative to silicon and the oxidized silicon, or selective chemical etching using an oxidizing solution.

6. The method of claim 1, further comprising thermally oxidizing the tunnel of the first combination.

7. The method of claim 1, wherein forming the hard mask comprises forming a polysilicon grid on the thin silicon dioxide layer and covering the polysilicon grid with a thin layer hard mask.

8. The method of claim 1, further comprising fabricating a CMOS device.

9. A method of fabricating a semiconductor device, the method comprising:

forming on a main surface of a silicon substrate, a stack comprising successively at least one first combination and one second combination, wherein each combination comprises, with reference to the substrate, a thin bottom layer of germanium, or a germanium and silicon alloy (SiGe), and a thin top layer of silicon;

forming on the thin top silicon layer of the second combination, a thin silicon dioxide layer that supports the layers of the stack on at least two opposite lateral sides of the stack;

forming a hard mask on the thin silicon dioxide layer so as to form two separate opposed areas on respective opposite sides of two opposite edges of the hard mask;

etching the thin silicon dioxide layer, the top silicon layer and at least part of the lower germanium or SiGe layer of the second combination in the two separate opposed areas;

selectively laterally etching the bottom germanium or SiGe layer of the second combination to form a tunnel;

thermally oxidizing the tunnel of the second combination;

etching the top silicon layer and at least part of the bottom germanium or SiGe layer of the first combination in the two separate opposed areas;

selectively laterally etching the bottom germanium or SiGe layer of the first combination to form a tunnel; and

filling the tunnel of the first combination with a solid dielectric material.

10. The method of claim 9, wherein the germanium and silicon SiGe alloy comprises an alloy formed of germanium and silicon such that Si_1-xGe_x (0<

x≦

1) and Si_1-xyGe_y (0<

x≦

0.95;

0<

y≦

0.05).

11. The method of claim 9, wherein forming the hard mask comprises forming a polysilicon grid on the thin silicon dioxide layer and covering the polysilicon grid with a thin layer hard mask.