Method of forming semiconductor device including interconnect barrier layers

• US 6,713,381 B2
• Filed: 01/18/2002
• Issued: 03/30/2004
• Est. Priority Date: 04/05/1999
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Venkatraman, Ramnath, Venkatesan, Suresh, Barr, Alexander L., Reber, Douglas M., Adetutu, Olubunmi, Clegg, David B., Anthony, Brian G., Crown, Stephen R., Greer, Stuart E., Cole, Rebecca G., Braeckelmann, Gregor
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US10/051,262
• Publication Number:
  US 20020093098A1
• Time in Patent Office: 802 Days
• Field of Search: 438/622, 438/618, 438/613-614, 438/627, 438/687, 438/685, 438/637-640, 438/643, 438/648
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/03009 for protecting parts during manufacture
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05157 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05172 : Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/0518 : Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05572 : the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 23/53233 : Copper alloys
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0496 : 6th Group
• CPC Class Codes: H01L 2924/0537 : 7th Group
• CPC Class Codes: H01L 2924/0538 : 8th Group
• CPC Class Codes: H01L 2924/0539 : 9th Group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Claims

1. A method of forming a semiconductor device comprising:

forming a first interconnect overlying a semiconductor device substrate;

forming a second interconnect overlying portions of the first interconnect, wherein the second interconnect is further characterized as a copper interconnect having a bond pad portion;

forming a conductive barrier layer over the bond pad portion;

forming an oxidation-resistant layer over the conductive barrier layer;

forming a passivation layer overlying the oxidation-resistant layer; and

forming a partial opening in the passivation layer, wherein a depth of the partial opening is less than a thickness of the passivation layer in a region of the passivation layer where the partial opening is formed;

forming a die coat layer over the passivation layer;

forming an opening in the die coat layer, wherein forming the opening in the die coat layer exposes the partial opening in the passivation layer and further includes partially removing the passivation layer about an edge region of the partial opening in the passivation layer;

etching through the partial opening in the passivation layer to expose the conductive barrier layer after forming the opening in the die coat layer; and

forming a pad limiting metal over the conductive barrier layer, wherein the pad limiting metal layer includes a chromium layer and wherein the chromium layer contacts the conductive barrier layer; and

forming a conductive bump over the pad limiting metal layer.

2. The method of claim 1, wherein a portion of the conductive barrier layers forms a laser-alterable connection between at least two conductive regions.

3. The method of claim 1, wherein the conductive barrier layer includes one selected from a group consisting of titanium and titanium nitride.

4. The method of claim 1 wherein the oxidation-resistant layer includes silicon nitride.

5. The method of claim 1, wherein the conductive barrier layer includes a refractory metal nitride.

6. The method of claim 1, wherein the conductive barrier layer includes a material selected from a group consisting of titanium, tantalum, tungsten, iridium, and nickel.

7. The method of claim 1, wherein the conductive barrier layer includes a combination of a refractory metal and a refractory metal nitride.

8. The method of claim 7, wherein the conductive barrier layer includes titanium and titanium nitride.

9. The method of claim 1, wherein the conductive barrier layer includes at least one of tantalum nitride, titanium tungsten nitride, titanium tungsten, tungsten nitride, molybdenum nitride, and cobalt nitride.

10. The method of claim 1, wherein the conductive barrier layer includes at least one of platinum, palladium, and nickel.

11. The method of claim 1, wherein the conductive barrier layer includes at least one of iridium, iridium oxide, ruthenium, ruthenium oxide, rhenium, rhenium oxide, osmium and osmium oxide.

12. The method of claim 1, wherein the oxidation-resistant layer includes nitrogen.

13. The method of claim 1, wherein the oxidation-resistant layer is a silicon layer.