Electrostatic discharge device for integrated circuits

• US 6,713,816 B1
• Filed: 06/27/2000
• Issued: 03/30/2004
• Est. Priority Date: 10/21/1997
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Wilkening, Wolfgang, Wolf, Heinrich
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/529,942
• Time in Patent Office: 1,372 Days
• Field of Search: 257/355, 257/361, 257/362
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

An ESD protection device for an integrated circuit, which is integrated in a semiconductor substrate of the integrated circuit, has a heavily doped p-region provided with a first connection electrode, a heavily doped n-region provided with a second connection electrode, a lightly doped p-region bordering on the heavily doped p-region, and a lightly doped n-region bordering on the heavily doped n-region and the lightly doped p-region in such a way that the lightly doped regions are arranged at least between the heavily doped regions. The distance which exists between the lightly doped p-region and the heavily doped n-region and which is determined by the lightly doped n-region is dimensioned in such a way that the depletion zone in the lightly doped n-region, which becomes larger as the blocking voltage applied to the connection electrodes increases, reaches the heavily doped n-region before the breakthrough voltage between the lightly doped n-region and the lightly doped p-region has been reached.

Claims

1. An ESD protection device for an integrated circuit which is integrated in a semiconductor substrate of said integrated circuit, comprising:

a heavily doped p-region provided with a first connection electrode;

a heavily doped n-region provided with a second connection electrode;

a lightly doped p-region bordering on said heavily doped p-region;

a lightly doped n-region bordering on said heavily doped n-region and said lightly doped p-region and having a first portion and a second portion; and

a heavily doped n-layer;

wherein said heavily doped n-region, said first portion of said lightly doped n-region and said lightly doped p-region form a lateral sequence of differently doped semiconductor regions adjacent a surface of said substrate;

wherein said lightly doped p-region, said second portion of said lightly doped n-region and said heavily doped n-layer form a vertical sequence of differently doped semiconductor regions;

wherein a lateral distance which exists between said lightly doped p-region and said heavily doped n-region and which is determined by said first portion of said lightly doped n-region is adjusted to be less than a distance which exists between said lightly doped p-region and said heavily doped n-layer and which is determined by said second portion of said lightly doped n-region such that a lateral breakthrough occurs between said lightly doped p-region and said heavily doped n-region before a vertical breakthrough occurs between said lightly doped p-region and said heavily doped n-layer, as a blocking voltage applied to said first and second connection electrodes increases;

wherein said lightly doped p-region is implemented as a p-well around said heavily doped p-region;

wherein said p-well is surrounded by said lightly doped n-region; and

wherein said lightly doped n-region is surrounded by a buried heavily doped n-layer.

2. The ESD protection device of claim 1, wherein a heavily doped n-region is provided in said lightly doped p-region between said lightly doped n-region and said heavily doped p-region, said heavily doped n-region being connected to said heavily doped p-region via said second connection electrode.

3. An ESD protection device for an integrated circuit which is integrated in a semiconductor substrate of said integrated circuit, comprising:

a heavily doped n-region provided with a first connection electrode;

a heavily doped p-region provided with a second connection electrode;

a lightly doped n-region bordering on said heavily doped n-region; and

a lightly doped p-region bordering on said heavily doped p-region and said lightly doped n-region and having a first portion and a second portion; and

a heavily doped p-layer;

wherein said heavily doped p-region, said first portion of said lightly doped p-region and said lightly doped n-region form a lateral sequence of differently doped semiconductor regions adjacent a surface of said substrate;

wherein said lightly doped n-region, said second portion of said lightly doped p-region and said heavily doped p-layer form a vertical sequence of differently doped semiconductor regions;

wherein a lateral distance which exists between said lightly doped n-region and said heavily doped p-region and which is determined by said first portion of said lightly doped p-region is adjusted to be less than a distance which exists between said lightly doped n-region and said heavily doped p-layer and which is determined by said second portion of said lightly doped p-region such that a lateral breakthrough occurs between said lightly doped n-region and said heavily doped p-region before a vertical breakthrough occurs between said lightly doped n-region and said heavily doped p-layer, as a blocking voltage applied to said connection electrodes increases;

wherein said lightly doped n-region is implemented as an n-well around said heavily doped n-region;

wherein said n-well is surrounded by said lightly doped p-region; and

wherein said lightly doped p-region is surrounded by a buried heavily doped p-layer.

4. The ESD protection device of claim 3, wherein a heavily doped p-region is provided in said lightly doped n-region between said lightly doped p-region and said heavily doped n-region, said heavily doped p-region being connected to said heavily doped n-region via said second connection electrode.