Reliable semiconductor device and method of manufacturing the same

• US 6,713,824 B1
• Filed: 12/14/1999
• Issued: 03/30/2004
• Est. Priority Date: 12/15/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akahori, Hiroshi, Katsui, Shuji, Mikata, Yuuichi
• Primary Examiner(s): Eckert, George
• Application Number:
  US09/459,913
• Time in Patent Office: 1,568 Days
• Field of Search: 257/407, 257/412, 438/197, 438/198, 438/257, 438/585
• US Class Current: 257/407
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same improved in reliability of a gate insulating film by increasing a total charge amount Qbd by suppressing a film stress of a gate electrode formed of a polysilicon film, to a low value. Since the film stress is closely related to a film formation temperature, it is possible to reduce the film stress lower than the conventional case by forming a film at as a high temperature as 640° C. or more. At this time, when the film stress decreases, the total charge amount Qbd regulating dielectric breakdown of the film increases, improving reliability of the gate insulating film. It is therefore possible to set the film stress of the gate electrode at 200 MPA or less in terms of absolute value by forming the gate electrode at 640° C. or more.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

source/drain regions formed in a surface of the substrate;

a gate insulating film disposed on a surface of the substrate between the source/drain regions; and

a gate electrode disposed on the gate insulating film, the gate electrode being set to have a film stress of 200 MPa or less in terms of absolute value, such that a total charge amount is 25 C/cm² or more, the total charge amount being an amount of electric charge passing through the gate insulating film when intrinsic dielectric breakdown of the gate insulating film takes place.

2. A device according to claim 1, wherein the gate electrode comprises a polysilicon film doped with an impurity.

3. A device according to claim 2, wherein the gate electrode consists essentially of the polysilicon film.

4. A device according to claim 2, wherein the film stress is a compressive stress.

5. A device according to claim 2, wherein the polysilicon film is a product formed by means of CVD process performed at a film formation temperature of 640°

C. or more.

6. A device according to claim 5, wherein the film formation temperature is 650°

C. or more.

7. A device according to claim 5, wherein the semiconductor substrate is rotated at a rotationally speed of 3000 rpm or more during the CVD process.

8. A device according to claim 1, wherein the gate insulating film comprises a silicon oxide film.

9. A device according to claim 8, wherein the gate insulating film consists essentially of the silicon oxide film.

10. A device according to claim 9, wherein the gate insulating film has a property such that the total charge amount is 25 C/cm² or more where the gate insulating film has a thickness of 8 nm and is supplied with an electric field of 12 MV/cm.

11. A non-volatile semiconductor memory device comprising:

a semiconductor substrate;

source/drain regions formed in a surface of the substrate;

a first gate insulating film disposed on a surface of the substrate between the source/drain regions;

a floating gate electrode disposed on the first gate insulating film, the floating gate electrode being set to have a film stress of 200 MPa or less in terms of absolute value, such that a total charge amount is 25 C/cm ² or more, the total charge amount being an amount of electric charge passing through the fist gate insulating film when intrinsic dielectric breakdown of the first gate insulating film takes place;

a second gate insulating film disposed on the floating gate electrode; and

a control gate electrode disposed on the gate insulating film.

12. A device according to claim 11, wherein the floating gate electrode comprises a polysilicon film doped with an impurity.

13. A device according to claim 12, wherein the floating gate electrode consists essentially of the polysilicon film.

14. A device according to claim 12, wherein the film stress is a compressive stress.

15. A device according to claim 12, wherein the polysilicon film is a product formed by means of CVD process performed at a film formation temperature of 640°

C. or more.

16. A device according to claim 15, wherein the film formation temperature is 650°

C. or more.

17. A device according to claim 15, wherein the semiconductor substrate is rotated at a rotational speed of 3000 rpm or more during the CVD process.

18. A device according to claim 11, wherein the first gate insulating film comprises a silicon oxide film.

19. A device according to claim 18, wherein the first gate insulating film consists essentially of the silicon oxide film.

20. A device according to claim 19, wherein the first gate insulating film has a property such that the total charge amount is 25 C/cm² or more where the first gate insulating film has a thickness of 8 nm and is supplied with an electric filed of 12 MV/cm.

21. A semiconductor device comprising:

a semiconductor substrate;

source/drain regions formed in a surface of the substrate;

a gate insulating film disposed on a surface of the substrate between the source/drain regions; and

a gate electrode disposed on the gate insulating film, the gate electrode being set to have a film stress of 200 MPa or less in terms of absolute value, in order to increase a total charge amount of electric charge passing through the gate insulating film when intrinsic dielectric breakdown of the gate insulating film takes place,

wherein the gate insulating film consists essentially of a silicon oxide film, and wherein the gate insulating film has a property such that the total charge amount is 25 C/cm² or more where the gate insulating film has a thickness of 8 nm and is supplied with an electric field of 12 MV/cm.

22. A non-volatile semiconductor memory device comprising:

a semiconductor substrate;

source/drain regions formed in a surface of the substrate;

a first gate insulating film disposed on a surface of the substrate between the source/drain regions;

a floating gate electrode disposed on the first gate insulating film, the floating gage electrode being set to have a film stress of 200 MPa or less in terms of absolute value, in order to increase a total charge amount of electric charge passing through the first gate insulating film when intrinsic dielectric breakdown of the first gate insulating film takes place;

a second gate insulating film disposed on the floating gate electrode; and

a control gate electrode disposed on the second gate insulating film,

wherein the first gate insulating film consists essentially of the silicon oxide film, and

wherein the first gate insulating film has a property such that the total charge amount if 25 C/cm² or more where the first gate insulating film has a thickness of 8 nm and is supplied with an electric field of 12 MV/cm.

23. A device according to claim 22, wherein the floating gate electrode consists essentially of a polysilicon film doped with an impurity, and the film stress is a compressive stress.