Low temperature co-fired ceramic-metal packaging technology

• US 6,713,862 B2
• Filed: 07/19/2002
• Issued: 03/30/2004
• Est. Priority Date: 12/13/1999
• Status: Expired due to Term

• Current Assignee: Lighting Science Group Corporation (Pegasus Capital Advisors, L.P.)
• Original Assignee: Lamina Ceramics, Inc.
• Inventors: Palanisamy, Ponnuswamy, Narayanaswamysreeram, Attiganal, Tormey, Ellen Schwartz, Thaler, Barry Jay, Connolly, John, Martinelli, Ramon Ubaldo, Prabhu, Ashok Narayan, Hammond, Mark Stuart, Mazzochette, Joseph
• Primary Examiner(s): Vigushin, John B.
• Assistant Examiner(s): CRUZ, LOURDES C
• Application Number:
  US10/199,418
• Publication Number:
  US 20030034564A1
• Time in Patent Office: 620 Days
• Field of Search: 257/706, 257/707, 257/712, 257/717, 257/720, 257/723, 257/724, 438/121, 438/122, 438/668, 438/700, 438/701, 438/703, 438/713, 438/738, 438/758, 438/778, 174/52.4, 174/252, 361/702
• US Class Current: 257/703
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01S 5/02251 using optical fibres
• CPC Class Codes: H01S 5/02325 Mechanically integrated components on mount members or optical micro-benches
• CPC Class Codes: H01S 5/02415 by using a thermo-electric cooler [TEC], e.g. Peltier element
• CPC Class Codes: H01S 5/02484 Sapphire or diamond heat spreaders

Abstract

Integrated packages incorporating multilayer ceramic circuit boards mounted on a metal support substrate can be used for temperature control by the metal support substrate. Various electronic components, as well as additional temperature control devices, can be connected to the circuit boards and to the metal support substrate to control or regulate the temperature of operation of the components. The integrated package can be hermetically sealed with a lid.

Claims

1. A low temperature cofired ceramic-metal (LTCC-M) system integrated package comprising:

a first circuit board comprising conductive traces;

a second circuit board comprising conductive traces and electronic components;

a first metal substrate supporting the second circuit board;

a second metal substrate connected to the first metal substrate via a heat pump;

wherein

the second circuit board is a ceramic circuit board;

the first circuit board is bonded over the second circuit board, to seal the electronic components on the second circuit board, with traces of the first circuit board connecting electronic components on the second circuit board; and

at least one of the components is a resistor.

2. The device of claim 1 wherein at least one of the resistors is a power resistor.

3. The device of claim 1 further comprising a flip chip mounted on the first metal substrate, and the first circuit board is bonded over the flip chip to hermetically seal the flip chip with traces of the first circuit board connecting the flip chip with components on the second circuit board.

4. The integrated package of claim 1 wherein the seal is a hermetic seal.

5. A low temperature cofired ceramic-metal (LTCC-M) system integrated package comprising:

a first circuit board comprising conductive traces;

a second circuit board comprising conductive traces and electronic components;

a first metal substrate supporting the second circuit board;

a second metal substrate connected to the first metal substrate via a heat pump;

wherein

the second circuit board is a ceramic circuit board;

the first circuit board is bonded over the second circuit board, to seal the electronic components on the second circuit board, with traces of the first circuit board connecting electronic components on the second circuit board; and

the first circuit board is a non-flexible circuit.

6. The device of claim 5 further comprising a flip chip mounted on the first metal substrate, and the first circuit board is bonded over the flip chip to hermetically seal the flip chip with traces of the first circuit board connecting the flip chip with components on the second circuit board.

7. The integrated package of claim 5 wherein the non-flexible circuit is bonded to the ceramic circuit board and the flip chip by solder bumps.

8. The integrated package of claim 5 wherein the non-flexible circuit comprises viewing holes for post soldering inspection of connections to the solder bumps.

9. The integrated package of claim 5 wherein the flip chip is electrically connected to the ceramic circuit board by the non-flexible circuit.

10. The integrated package of claim 5 wherein the seal is a hermetic seal.