Logic state transition sensor circuit

• US 6,714,049 B2
• Filed: 08/12/2002
• Issued: 03/30/2004
• Est. Priority Date: 08/10/2001
• Status: Expired due to Fees

• Current Assignee: Shakti Systems Inc.
• Original Assignee: Shakti Systems Inc.
• Inventors: McShane, Erik A., Shenai, Krishna
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/217,895
• Publication Number:
  US 20030034818A1
• Time in Patent Office: 596 Days
• Field of Search: 326/82, 326/11, 326/36, 326/88, 324/111
• US Class Current: 326/82
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Claims

1. A logic state transition sensor circuit comprising:

a sensing circuit coupled to an electrical node, the sensing circuit being operable to generate a pulse in response to a logic state transition at the electrical node; and

a recording circuit coupled to the sensing circuit, the recording circuit being operable to accumulate a capacitive charge in response to each pulse generated by the sensing circuit,

wherein the accumulated capacitive charge is representative of a number of logic state transitions sensed at the electrical node.

2. The logic state transition sensor circuit of claim 1, wherein in response to each pulse generated by the sensing circuit, the recording circuit accumulates an incremental capacitive charge.

3. The logic state transition sensor circuit of claim 2, wherein the incremental capacitive charge is accumulated using charge accumulation based on a ratio of capacitors.

4. The logic state transition sensor circuit of claim 1, wherein the logic state transition is selected from the group consisting of a change in voltage, a rising edge of a signal, and a falling edge of a signal.

5. The logic state transition sensor circuit of claim 1, wherein the sensing circuit comprises a pulse generator being operable to generate the pulse in response to the logic state transition at the electrical node.

6. The logic state transition sensor circuit of claim 1, wherein the sensing circuit comprises:

an input terminal coupled to the electrical node;

a delay flip-flop coupled to the input terminal, wherein the delay flip-flop produces a first and a second output, wherein the first output is a first logical value of a signal received at the input terminal and the second output is a second logical value that is the logical complement of the first logical value;

a first delay buffer coupled to the first output of the delay flip-flop and a second delay buffer coupled to the second output of the delay flip-flop;

a voltage inverting circuit coupled to the input terminal and a voltage non-inverting circuit coupled to the input terminal;

a first NAND gate having input terminals connected to an output of the voltage inverting circuit and to an output of the first delay buffer; and

a second NAND gate having input terminals connected to an output of the voltage non-inverting circuit and an output of the second delay buffer,

wherein the first NAND gate and the second NAND gate each have outputs that are connected to inputs of a third NAND gate, wherein the third NAND gate produces a logic low value when a signal received at the input terminal reaches a steady-state value.

7. The logic state transition sensor circuit of claim 6, wherein the voltage inverting circuit and the voltage non-inverting circuit are implemented with components selected from the group consisting of CMOS inverters, operational amplifiers, and analog voltage comparators.

8. The logic state transition sensor circuit of claim 1, wherein the recording circuit comprises an output terminal being operable to produce an output voltage potential representative of the number of logic state transitions sensed.

9. The logic state transition sensor circuit of claim 1, wherein the recording circuit accumulates the charge within a first capacitor and transfers the charge from the first capacitor to a second capacitor according to a ratio of the first capacitor and the second capacitor.

10. The logic state transition sensor circuit of claim 1, wherein the recording circuit comprises a logic shaping circuit coupling the sensing circuit and the recording circuit, wherein the logic shaping circuit outputs a non-inverting voltage output with an abrupt transition between a minimum voltage potential and a maximum voltage potential.

11. The logic state transition sensor circuit of claim 1, wherein the recording circuit comprises a current source being operable to charge a first capacitor in response to each pulse generated by the sensing circuit.

12. The logic state transition sensor circuit of claim 1, wherein the recording circuit comprises:

a first capacitor connected to an output of the sensing circuit;

a second capacitor connected to the first capacitor through a first switch;

a third capacitor connected to the second capacitor through a second switch;

a voltage inverting circuit having an input connected to the output of the sensing circuit and an output connected to a negative-logic input of the first switch and to a positive-logic input of the second switch; and

a voltage non-inverting circuit having an input connected to the output of the sensing circuit and an output connected to a positive-logic input of the first switch and to a negative-logic input of the second switch,

wherein when the sensing circuit outputs the pulse, the first capacitor charges the second capacitor, and after a momentary time period the second capacitor transfers its charge to the third capacitor.

13. The logic state transition sensor circuit of claim 12, further comprising a logic driver circuit inserted between the output of the sensing circuit and the first capacitor.

14. The logic state transition sensor circuit of claim 12, wherein the voltage inverting circuit and the voltage non-inverting circuit are implemented using components selected from the group consisting of CMOS inverters, operational amplifiers, and analog voltage comparators.

15. The logic state transition sensor circuit of claim 1, further comprising a reset mechanism coupled to the recording circuit, wherein the reset mechanism dissipates the accumulated capacitive charge at the recording circuit.

16. A logic state transition sensor comprising:

a sensing circuit coupled to an electrical node, the sensing circuit being operable to generate a momentary output signal in response to a logic state transition at the electrical node; and

a recording circuit coupled to the sensing circuit, the recording circuit being operable to keep count of each momentary output signal generated by the sensing circuit,

wherein the recording circuit outputs an output signal representative of a number of logic state transitions sensed at the electrical node.

17. The logic state transition sensor of claim 16, wherein the recording circuit keeps count of each momentary output signal generated by the sensing circuit by accumulating a charge on a first capacitor in response to each momentary output signal and transferring the charge from the first capacitor to a second capacitor based on a ratio of capacitance values of the first and second capacitors.

18. The logic state transition sensor of claim 17, wherein the capacitance value of the second capacitor is larger than the capacitance value of the first capacitor.

19. The logic state transition sensor of claim 18, wherein the second capacitor accumulates an incremental charge based on the transfer of charge from the first capacitor.

20. A method of sensing logic state transitions comprising:

generating a momentary signal in response to a logic state transition at an electrical node;

accumulating a capacitive charge in response to each momentary signal generated; and

outputting an output signal representative of a number of logic state transitions sensed at the electrical node.

21. The method of claim 20, wherein generating the momentary signal in response to the logic state transition at an electrical node comprises producing a pulse signal.

22. The method of claim 20, wherein accumulating the capacitive charge comprises recording the logic state transition based at least on a ratio of capacitors.

23. The method of claim 22, wherein recording the logic state transition based at least on a ratio of capacitors comprises:

accumulating a charge on a first capacitor; and

transferring the charge to a second capacitor after a momentary time representative of a propagation time of the momentary signal so as to incrementally increase the second capacitor'"'"'s charge.

24. The method of claim 23, wherein outputting the output signal representative of the number of logic state transitions sensed at the electrical node comprises outputting the second capacitor'"'"'s charge.

25. The method of claim 20, further comprising generating a steady-state signal after generating the momentary signal in response to the logic state transition at the electrical node.