Active current bias network for compensating hot-carrier injection induced bias drift

• US 6,714,081 B1
• Filed: 09/11/2002
• Issued: 03/30/2004
• Est. Priority Date: 09/11/2002
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Xu, Jie
• Primary Examiner(s): Choe, Henry
• Application Number:
  US10/241,081
• Publication Number:
  US 20040046609A1
• Time in Patent Office: 566 Days
• Field of Search: 330/296, 330/288, 330/290, 323/315, 323/316
• US Class Current: 330/296
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit

Abstract

An active current bias network that compensates for Hot-Carrier Injection (HCI) induced bias drift, a common phenomenon existing in Metal-Oxide Semiconductor (MOS) transistors and especially in Laterally Diffused MOS (LDMOS) transistors. The active bias network of the present invention first senses the bias current flowing in the targeted transistor and then compares the bias current in the targeted transistor with a stable reference current. The difference between the bias current in the targeted transistor and the reference current is then utilized to adjust the bias of the targeted transistor via a current mirror feedback circuit. The bias current of the targeted transistor then is stable independent of any HCI induced bias changes and changes due to other adverse causes. The sensing MOS transistor used for monitoring bias current is operated in the triode region and has minimum effect on the performance of the targeted transistor.

Claims

1. An active bias current network, comprising:

a target transistor;

a reference transistor;

a current source;

a current sensor comprising a first current mirror having two transistors biased in the triode region and a second current mirror coupled between said first current mirror and said current source, wherein said second current mirror is comprised of two transistors biased in the saturation region; and

a feedback control, said current sensor is coupled to said reference transistor, said current source is connected to said current sensor and said feedback control, said feedback control is coupled to said target transistor and said reference transistor, wherein said feedback control is a transistor coupled to said reference transistor and said target transistor to form a third current mirror.

2. The active bias network of claim 1, wherein said first current mirror is further comprised of an operational amplifier coupled between said two transistors biased in the triode region.

3. The active bias network of claim 1, wherein said first current mirror is further comprised of a biasing transistor coupled to said operational amplifier and said second current mirror.

5. The active bias network of claim 1, further comprising current equalizing means to provide that said two transistors biased in the triode region of said first current mirror each provide an equivalent level of current.

6. The active bias network of claim 5, wherein said current equalizing means is comprised of an operational amplifier coupled between said two transistors biased in the triode region.

7. The active bias network of claim 5, wherein said current equalizing means is further comprised of a biasing transistor coupled to said operational amplifier and said second current mirror.

4. An active bias current network, comprising:

a target transistor having a bias current;

reference means to simulate said bias current;

current sensing means to monitor said bias current, said current sensing means comprising;

a first current mirror having two transistors biased in the triode region;

a second current mirror having two transistors biased in the saturation region; and

constant current means to provide a constant current source; and

feedback means to adjust a bias of said target transistor and said reference transistor, said current sensing means is coupled to said reference means, said constant current means is connected to said current sensing means and said feedback means, wherein said feedback means is a transistor coupled to said reference means and said target transistor to form a third current mirror.

8. A method for regulating the bias current in a transistor, comprising the steps of:

replicating a bias current from a target transistor with a reference transistor;

biasing a first current mirror into a triode region;

sensing said bias current with said first current mirror;

comparing said bias current to a reference current;

determining a current difference between said bias current and said reference current;

adjusting a bias across said target transistor and said reference transistor using said current difference between said bias current and said reference current;

equalizing the input and output currents of said first current mirror; and

buffering the output of said first current mirror from said reference current with a second current mirror.

9. The method of regulating the bias current in a transistor of claim 8, comprising the further step of biasing a pair of transistors forming said second current mirror into a saturation region.

10. An active bias current network for stabilizing the bias current in a target transistor, comprising:

a reference transistor;

a first current mirror coupled to said reference transistor, said first current mirror comprising;

a transistor pair biased in a triode region;

an operational amplifier having a pair coupled between said transistor pair; and

a biasing transistor connected to an output of said operational amplifier;

a second current mirror coupled to said biasing transistor, said second current mirror comprised of a transistor pair biased in a saturation mode;

a reference current source coupled to said second current mirror; and

a feedback transistor coupled between said reference current, said second current mirror, and said reference transistor and said target transistor.

11. A method of regulating the bias current in a transistor, comprising the steps of:

producing a bias reference current;

varying said bias reference current with hot carrier injection;

monitoring said bias reference current with a current sensor;

comparing said bias reference current to a constant reference current;

determining a current difference between said bias reference current and said constant reference current; and

adjusting a bias on said transistor using said current difference.