Parallel channel programming scheme for MLC flash memory

• US 6,714,457 B1
• Filed: 09/03/2002
• Issued: 03/30/2004
• Est. Priority Date: 09/19/2001
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Tsao, Hsing-Ya, Lee, Peter W., Hsu, Fu-Chang
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/233,642
• Time in Patent Office: 574 Days
• Field of Search: 365/185.03, 365/185.17, 365/185.22, 365/185.28
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5622 Concurrent multilevel programming of more than one cell

Abstract

In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.

Claims

1. A method of parallel programming flash multiple level cell (MLC) memory comprising

a) coupling a plurality of voltages simultaneously to both the bit line and the source line of a plurality of memory cells for a predetermined amount of time,

b) coupling a high word line voltage to a word line connecting to said plurality of memory cells for said predetermined amount of time,

c) programming said plurality of memory cells to a plurality of threshold voltages wherein said threshold voltage of said memory cell coupled to a larger bit line voltage is smaller than said threshold voltage of said memory cell coupled to a smaller bit line voltage,

d) verifying the programming of said N memory cells.

2. The method of claim 1, wherein said source line is floating.

3. The method of claim 1, wherein each of said plurality of voltages coupled to said plurality of bit lines of the plurality of memory cells are chosen to produce the plurality of threshold voltages in which said the plurality of threshold voltages are attained during a single program duration at a fixed word line voltage.

4. A method of parallel programming four flash memory multiple level cells (MLC) comprising:

a) coupling a first voltage to both a bit line and a source line of a first memory cell,

b) coupling a second voltage larger than said first voltage to both the bit line and the source line of a second memory cell,

c) coupling a third voltage larger than said second voltage to both the bit line and the source line of a third memory cell,

d) coupling a fourth voltage larger than said third voltage to both the bit line and the source line of a fourth memory cell,

e) coupling a word line voltage of high value to a word line coupled to control gates of said first, second, third and fourth memory cells,

f) programming said first memory cell to a first threshold voltage level, said second memory cell to a second threshold voltage level which is smaller than said first threshold voltage level, said third memory cell to a third threshold voltage level which is smaller than said second threshold voltage level, and said fourth memory cell to a fourth threshold voltage level which is smaller than said third threshold voltage level,

g) verifying said first memory cell is programmed to said first threshold voltage level, said second memory cell is programmed to said second threshold voltage level, said third memory cell is programmed to said third threshold voltage level, and said forth memory cell is programmed to said fourth threshold voltage level.

5. The method of claim 4, further comprising:

a) coupling a plurality of voltages to both the bit line and the source line of a plurality of memory cells,

b) coupling a high word line voltage to a word line connecting to said N memory cells,

c) programming said plurality of memory cells to a plurality of threshold voltages wherein said threshold voltage of said memory cell coupled to a larger bit line voltage is smaller than said threshold voltage of said memory cell coupled to a smaller bit line voltage,

d) verifying the programming of said plurality of memory cells.

6. The method of claim 5, wherein programming the plurality of memory cells to the plurality of threshold voltages of predetermined values is accomplished simultaneously by coupling said plurality of voltages of a plurality of predetermined values to bit lines and source lines of said plurality of memory cells during said predetermined amount of time when said word line voltage is coupled to said word line.

7. The method of claim 4, wherein verifying the programming of said memory cells is done by checking the voltage threshold level of the cells, and changing a corresponding bit line voltage to a program inhibit voltage level when the cells have been detected to be programmed.

8. The method of claim 4, wherein said first and second source lines are floating.

9. The method of claim 4, wherein said word line voltage coupled to said word line varies from a low initial value to a high final value during parallel programming of said memory cells.

10. The method of claim 9, wherein said first voltage varies from a first low value to a first high value and said second voltage varies from a second low value to a second high value during parallel programming of said memory cells.

11. The method of claim 5, wherein programming the plurality of memory cells to the plurality of threshold voltage levels having predetermined values is accomplished simultaneously by coupling the plurality of voltages of a plurality of predetermined values to bit lines and source lines of said N memory cells during said predetermined amount of time when said word line voltage is coupled to said word line.

12. The method of claim 11, wherein said source lines are floating.

13. The method of claim 11, wherein said word line voltage coupled to said word line varies from a low initial value to a high final value during parallel programming of said memory cells.

14. The method of claim 13, wherein said plurality of voltages vary from an initial low value to a final high value during parallel programming of said memory cells.

15. The method of claim 4, wherein programming a plurality of memory cells to a same threshold voltage level is accomplished simultaneously by coupling the plurality of voltages of a same value to bit lines and source lines of said plurality of memory cells during said predetermined amount of time when said word line voltage is coupled to said word line.

16. The method of claim 15, wherein said source lines are floating.

17. The method of claim 15, wherein said word line voltage coupled to said word line varies from a low initial value to a high final value during parallel programming of said memory cells.

18. The method of claim 17, wherein said plurality of voltages vary from a same low value to a same high value during parallel programming of said memory cells.

19. A parallel programming means for a multiple level cell (MLC) flash memory array, comprising:

a) a means for coupling a first positive voltage to a first bit line connected to a first MLC flash memory cell to be programmed,

b) a means for coupling a second positive voltage to a second bit line connected to a second MLC flash memory cell to be programmed,

c) a means for coupling a third positive voltage of high value to a word line connected to said first and second MLC flash memory cells,

d) a means for activating said first, second and third positive voltages simultaneously for a predetermined amount of time to program in parallel said first and second MLC flash memory cells,

e) a means for verifying a threshold voltage level of said first and second flash MLC memory cells, and for inhibiting from further programming cells that have reach a predetermined threshold voltage level.

20. The parallel programming means of claim 19, wherein said first and second positive voltages and said third positive voltage combine to produce a channel voltage in said first and second MLC flash memory cell that is of a value necessary to program simultaneously said predetermined threshold voltage level for each said memory cell within a predetermined amount of time.

21. The parallel programming means of claim 19, further comprising means for coupling a plurality of positive voltages to a plurality of bit lines connected to a plurality of memory cells that are connected to said word line and to program in parallel said plurality of memory cells by simultaneously activating said plurality of positive voltages and said third positive voltage.

22. The parallel programming means of claim 21, wherein said third positive voltage varies from a low initial value to a high final value.

23. The parallel programming means of claim 22, wherein said plurality of positive voltages vary from a plurality of low initial values to a plurality of high initial values.

24. The parallel programming means of claim 22, wherein said plurality of positive voltages comprise a number of positive voltages that are a same value.

25. A means for programming an MLC memory array, comprising:

a) a means for coupling bit line voltages to cells to be programmed,

b) a means for coupling a word line voltage of high positive value to said cells to be programmed,

c) a means for programming said cells in parallel by activating simultaneously for a predetermined amount of time a plurality of said bit line voltages and said word line voltage,

d) a means for verifying a threshold voltage level of said cells during programming and inhibiting said cells from programming.

26. The means of claim 25, wherein said bit line voltages comprise a plurality of positive voltages of different values.

27. The means of claim 25, wherein said word line voltage varies from a low initial value to a high final value during programming of said cells.

28. The means of claim 27, wherein said bit line voltages start at a value lower than a final value during programming of said cells.

29. The means of claim 25, wherein bit line voltages combined with said word line voltage produce a channel voltage that determines the threshold voltage level of the cells being programmed.

30. The means of claim 25, wherein cells being programmed are inhibited from further programming when said threshold voltage level is at a predetermined value.

31. The means of claim 25, wherein said bit line voltages and said word line voltage combine to produce a channel voltage in said cells that is of a value necessary to program simultaneously a predetermined threshold voltage level for each cell within a predetermined amount of time.

32. A system for parallel programming a flash multiple level cell (MLC) memory, comprising:

a) a word line selected and coupled to a high positive voltage for a predetermined amount of time,

b) a plurality of positive voltages,

c) a first bit line data buffer connecting a first positive voltage of said plurality of positive voltages to a first bit line for said predetermined amount of time,

d) a second bit line data buffer connecting a second positive voltage of said plurality of positive voltages to a second bit line for said predetermined amount of time,

e) a first cell selected by said word line and said first bit line programmed to a first threshold voltage level,

f) a second cell selected by said word line and said second bit line programmed to a second threshold voltage level.

33. The system of claim 32, wherein said first bit line voltage and said word line high positive voltage creates a first channel voltage necessary to program a first cell to a first threshold voltage level, and said second bit line voltage and said word line high positive voltage creates a second channel voltage necessary to program a second cell to a second threshold voltage level simultaneously during said predetermined amount of time.

34. The system of claim 32, further comprising a plurality of bit line data buffers that connect said plurality of positive voltages to a plurality of bit lines for said predetermined amount of time to program a plurality of memory cells to a plurality of threshold voltage levels simultaneously when selected by said word line and said plurality of bit lines.

35. The system of claim 34, wherein said plurality of positive voltages connected to said plurality of bit lines combine with the word line high positive voltage to create a plurality of channel voltages to program said plurality of memory cells to said plurality of threshold voltage levels simultaneously during said predetermined amount of time.

36. The system of claim 34, wherein said plurality of positive voltages are a mixture of voltages having a same value and a different value.