Integrated services digital broadcasting deinterleaver architecture
First Claim
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1. An apparatus comprising:
- a memory having a plurality of memory locations accessed by a plurality of addresses;
a write pointer configured to write data to said memory in response to a sequence of write addresses generated in response to a first control signal;
a read pointer configured to read data from said memory in response to a sequence of read addresses generated in response to a second control signal; and
a control circuit configured to generate (i) said first control signal, and (ii) said second control signal, wherein the order said data is read from said memory comprises a de-interleaved pattern with respect to the order said data is written to said memory.
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Abstract
An apparatus comprising a memory, a write pointer, a read pointer and a control circuit. The memory may have a plurality of memory locations accessed by a plurality of addresses. The write pointer may be configured to write data to the memory in response to a sequence of write addresses generated in response to a first control signal. The read pointer may be configured to read data from the memory in response to a sequence of read addresses generated in response to a second control signal. The control circuit may be configured to generate (i) the first control signal, and (ii) the second control signal. The order data is read from said memory may comprise a de-interleaved pattern with respect to the order the data is written to the memory.
8 Citations
20 Claims
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1. An apparatus comprising:
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a memory having a plurality of memory locations accessed by a plurality of addresses;
a write pointer configured to write data to said memory in response to a sequence of write addresses generated in response to a first control signal;
a read pointer configured to read data from said memory in response to a sequence of read addresses generated in response to a second control signal; and
a control circuit configured to generate (i) said first control signal, and (ii) said second control signal, wherein the order said data is read from said memory comprises a de-interleaved pattern with respect to the order said data is written to said memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17)
said memory comprises L sections; and
each of said L sections comprises an I×
N array.
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12. The apparatus according to claim 10, wherein:
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said memory comprises L sections; and
each of said sections comprises an I×
M array, where M is (i) an integer greater than N and (ii) evenly divisible by I.
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17. The method according to claim 10, wherein said first control signal is generated such that:
during a first round of writing, said sequence of write addresses is described by a first equation expressable as
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13. An apparatus comprising:
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means for storing data in a plurality of memory locations accessed by a plurality of addresses;
means for writing data to said memory locations in response to a sequence of write addresses generated in response to a first control signal;
means for reading data from said memory locations in response to a sequence of read addresses generated in response to a second control signal; and
means for generating (i) said first control signal, and (ii) said second control signal, wherein the order said data is read from said memory locations comprises a de-interleaved pattern with respect to the order said data is written to said memory locations.
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14. A method for de-interleaving integrated services digital broadcast super frames comprising the steps of:
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(A) writing data to a memory in response to a sequence of write addresses generated in response to a first control signal;
(B) reading data from said memory in response to a sequence of read addresses generated in response to a second control signal; and
(C) generating (i) said first control signal, and (ii) said second control signal, wherein the order data is read from said memory comprises a de-interleaved pattern with respect to the order said data is written to said memory. - View Dependent Claims (15, 16, 18, 19, 20)
during a first round of reading, said sequence of read addresses is described by a first equation expressable as
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19. The method according to claim 14, wherein said first control signal and said second control signal are generated such that:
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during a first round, said sequence of write addresses is described by a first equation expressable as write_address(i)=write_pos/I+write_pos%I×
M andsaid sequence of read addresses is described by a second equation expressable as read_address(i)=read_pos; and
during a second round, said sequence of write addresses is described by a third equation expressable as write_address(i)=write_pos%M/I+write_pos%I×
M/I+write_pos/M×
M andsaid sequence of read addresses is described by a fourth equation expressable as read_address(i)=index%(M/I)+index/(M/I)×
M+frame×
(M/I), whereM=(N+I−
1)/I×
I,frame=i/(N×
L),slot=i%(N×
L)/N,index=i%(N×
L)%N,write_pos=(frame×
N)+index,read_pos=(frame×
M)+index,i is a sequence number of a data byte in one of said super frames, and said super frames comprise a number I of frames, each of said frames comprises a number L of slots, each of said slots comprises a number N of bytes, I, L and N are integers, and said first and second rounds are repeated continuously.
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20. The method according to claim 14, further comprising:
providing said memory comprising L sections, wherein each of said L sections comprises an I×
M array, where M is (i) an integer greater than N and (ii) evenly divisible by I, I represents a number of frames in each of said super frame, L represents a number of slots in each of said frames, N represents a number of bytes in each of said slots, and I, L and N are integers.
Specification
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsMogre, Advait, Qian, Cheng
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Primary Examiner(s)Tran, Khai
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Application NumberUS09/477,317Time in Patent Office1,547 DaysField of Search375/341, 375/340, 375/316, 714/752, 714/751, 714/784, 714/701US Class Current375/341CPC Class CodesH03M 13/2703 the interleaver involving a...H03M 13/276 Interleaving address genera...H04L 1/0071 Use of interleaving interle...
