Method and system for over-run protection in a message passing multi-processor computer system using a credit-based protocol

• US 6,715,008 B2
• Filed: 04/07/1999
• Issued: 03/30/2004
• Est. Priority Date: 05/08/1998
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shimizu, Takeshi
• Primary Examiner(s): Park, Ilwoo
• Assistant Examiner(s): KIM, HAROLD J
• Application Number:
  US09/287,650
• Publication Number:
  US 20020178306A1
• Time in Patent Office: 1,819 Days
• Field of Search: 710/37, 710/56, 710/42, 710/17, 710/19, 710/29, 710/34, 710/52, 709/229, 709/234, 709/235, 709/240, 709/248, 709/201, 709/206, 709/207, 709/215
• US Class Current: 710/56
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/39 Credit based
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

In a multi-processor computer system, a message receive unit using a shared buffer pool and a set of per-node credit registers in each processor node. The buffer stores incoming messages received from the sending nodes. The credit registers prevent a sending node from using more than its allocated share of the buffer pool and thus prevent the buffer pool from overflowing. Because the buffer pool of the receiving node does not overflow, the receiving node can continue to communicate with other nodes.

Claims

1. A message passing computer system, comprising:

an interconnection;

a plurality of multi-processor nodes connected to said interconnection; and

a credit-based message receive unit coupled to said interconnection for controlling passage of messages through said multi-processor nodes, the message receive unit including a message buffer coupled to a plurality of credit registers;

wherein the size of said buffer satisfies the condition;

2. The computer system of claim 1 wherein said buffer is constituted by a FIFO having a set of pointers for read/write access.

3. The computer system of claim 1 wherein each of said credit registers in a receiving node corresponds to a sending node.

4. The computer system of claim 3 wherein a value in said credit registers controls writing into said buffer.

5. The computer system of claim 4 wherein said value constitutes a maximum number of messages that the receiving node can receive from the sending node.

6. The computer system of claim 4, wherein the value represents the number of packets that can be written to a portion from a send node corresponding to the credit register.

7. The computer system of claim 4 wherein accessing messages in said buffer controls said value in said credit registers.

8. The computer system of claim 7 wherein said value is preset.

9. The computer system of claim 8 wherein each of said processor nodes comprises at least one processor end a memory.

10. The computer system of claim 9 wherein said buffer and said credit registers are part of a mesh coherence unit in each of said processor nodes.

11. The computer system of claim 1, wherein credit values associated with the credit-based message receive unit are only positive or zero.

12. The computer system of claim 1, wherein a send node cannot write to portions of the buffer allocated to other send nodes.

13. The computer system of claim 1 wherein said message receive unit comprises a multiplexer coupled to a decoder and to the plurality of credit registers.

14. A computer communication method in a multi-processor node computer system, comprising the steps of:

using a buffer for temporarily storing messages from at least one sending node to a receiving node;

using credit values stored in credit registers, each credit value corresponding to a respective one of the at least one sending node and controlling writing incoming messages from the at least one sending node into said buffer; and

determining the number of accesses of the at least one sending node to said buffer in order to adjust said credit value corresponding to the at least one sending node;

wherein said credit value in each of said plurality of credit registers determines the maximum number of messages that a receiving node can receive from the corresponding sending node.

15. The method of claim 14 comprising the further step of using a sending node ID to select a credit register corresponding to the sending node.

16. The method of claim 14 comprising the further step of determining the arrival of a message by receiving an interrupt signal or by periodically polling pointer registers of said buffer.

17. The method of claim 14 comprising the further step of using the credit value of a sending node in determining whether to discard an incoming message from said sending node.

18. The method of claim 14, comprising the further step of, when a message is discarded because of a lack of credits, either generating an interrupt, or generating an overflow signal, or logging overflow information.

19. A system comprising:

A) an interconnect;

B) a plurality of multiprocessor nodes connected to the interconnect, including at least

1) a bus,

2) a plurality of processors having at least a cache connected to the bus,

3) an input/output unit connected to the bus,

4) a memory unit, and

5) a mesh coherence unit connected to the bus, having at least

a) a memory controller for controlling the memory unit, and

b) a credit based receive unit having at least

i) an input for receiving a packet from the interconnect,

ii) a buffer coupled to the input for receiving,

iii) a decoder, coupled to the input for receiving, for decoding an identification of the packet,

iv) a credit adjustment logic unit coupled to the decoder and contents of the buffer, which, based on the decoding and the contents of the buffer creates a signal to adjust credit,

v) a bank of credit registers having a credit register whose credit is adjusted based on the signal to adjust credit, for returning signals to the credit adjustment logic unit so that the credit register whose credit is adjusted corresponds to a sending unit,

vi) a multiplexer coupled to the decoder and to the bank of credit registers for determining, based on the decoding, and passing, the credit value associated with the credit register whose credit is adjusted,

vii) a credit evaluator for evaluating the credit value that was passed by comparing the credit value to a value corresponding to no credits left to determine if credits remain, and

viii) a read/write control unit that is coupled to the buffer and to the credit evaluator and that uses results of the evaluating to determine whether to allow the packet to be written to the buffer;

c) the credit adjustment logic unit being coupled to the read/write control unit to recredit credit registers depending on whether a packet is read, not read, written, or not written to the buffer.

20. A system comprising:

a multiprocessor computer; and

a message passing system within the multiprocessor computer for passing messages between processors of the multiprocessor computer, the message passing system including at least

an interconnection,

a plurality of multi-processor nodes connected to said interconnection, each multi-processor node having a multiple processors, and

a credit-based message receive unit coupled to said interconnection for controlling passage of messages through said multi-processor nodes, the message receive unit including a message buffer coupled to a plurality of credit registers;

wherein the size of said buffer satisfies the condition;