System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation

• US 6,715,091 B1
• Filed: 04/10/2000
• Issued: 03/30/2004
• Est. Priority Date: 04/10/2000
• Status: Expired due to Term

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Kundu, Sandip
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/546,096
• Time in Patent Office: 1,450 Days
• Field of Search: 713/300, 713/323, 713/324, 323/222
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive.

Claims

1. A computer processor system having:

a plurality of memory storage elements; and

interconnection elements, responsive to detecting which of normal operation or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation by the processor.

2. The system of claim 1, wherein the interconnection elements are connected to inputs of the memory storage elements.

3. The system of claim 2, wherein the interconnection elements are operable to connect the memory storage elements in at least one series-connected chain, where an input of each memory storage element is connected to an output of one adjacent memory storage element during at least one of said configurations.

4. The system of claim 3, further comprising a storage device, and a switching element operable to connect a final memory storage element in the chain to said storage device.

5. The system of claim 4, further comprising a clocking signal line connected to the memory storage elements to cause data in the memory storage elements to pass serially through the chain and into the storage device.

6. The system of claim 3, further comprising a switching element operable to connect an initial memory storage element in the chain to a storage device.

7. The system of claim 6, further comprising a clocking signal line connected to the memory storage elements to cause data in the storage device to enter the first memory storage element and then pass serially through the chain.

8. The system of claim 2, wherein the interconnection elements are operable to connect the memory storage elements to form a plurality of parallel connected chains.

9. The system of claim 8, further comprising a storage device, a plurality of additional switching elements, each operable to connect a final memory storage element in one of the chains to deliver data to said storage device.

10. The processor of claim 8, further comprising a plurality of switching elements, each operable to connect an initial memory storage element in one of the chains to receive data from a storage device.

11. The processor of claim 1, further comprising a control circuit connected to deliver a control signal that activates the interconnection elements.

12. The processor of claim 11, where the control circuit is configured to assert the control signal just before power is removed from the processor.

13. The processor of claim 11, where the control circuit is configured to assert the control signal just after power is restored to the processor.

14. A method for use in a computer system having a processor, the method comprising:

arranging a plurality of memory storage elements in the processor into a first configuration during normal operation of the processor; and

rearranging the memory storage elements into a second configuration upon entering a low-power mode of operation of the processor.

15. The method of claim 14, wherein said rearranging the memory storage elements includes interconnecting the memory storage elements to form at least one series-connected chain.

16. The method of claim 15, further comprising passing data serially through the chain into a storage device.

17. The method of claim 16, further comprising removing power from the processor after passing data serially through the chain.

18. A method comprising:

restoring power to a processor;

arranging a plurality of memory storage elements in the processor into a first configuration in which the memory storage elements form a chain;

loading data from a storage device into a first memory storage element in the chain; and

passing the data through the chain.

19. The method of claim 18, further comprising thereafter rearranging the memory storage elements into a second configuration for normal operation of the processor.

20. A computer system comprising:

a processor having a plurality of memory storage elements; and

interconnection elements, responsive to detecting which of normal or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation of the processor and

a storage device coupled to exchange data with the processor;

a power supply connected to supply power to the processor during the normal operation and to withhold power from the processor during the low-power mode of operation.

21. The system of claim 20, wherein the interconnection elements are operable to arrange the memory storage elements into a chain.

22. The system of claim 20, further comprising at least one additional interconnection element operable to connect a final memory storage element in the chain to the storage device.

23. The system of claim 22, further comprising a clocking signal connected to cause data to pass serially through the chain and into the storage device.