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System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation

  • US 6,715,091 B1
  • Filed: 04/10/2000
  • Issued: 03/30/2004
  • Est. Priority Date: 04/10/2000
  • Status: Expired due to Term
First Claim
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1. A computer processor system having:

  • a plurality of memory storage elements; and

    interconnection elements, responsive to detecting which of normal operation or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation by the processor.

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