System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation
First Claim
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1. A computer processor system having:
- a plurality of memory storage elements; and
interconnection elements, responsive to detecting which of normal operation or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation by the processor.
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Abstract
A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive.
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Citations
23 Claims
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1. A computer processor system having:
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a plurality of memory storage elements; and
interconnection elements, responsive to detecting which of normal operation or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation by the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for use in a computer system having a processor, the method comprising:
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arranging a plurality of memory storage elements in the processor into a first configuration during normal operation of the processor; and
rearranging the memory storage elements into a second configuration upon entering a low-power mode of operation of the processor. - View Dependent Claims (15, 16, 17)
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18. A method comprising:
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restoring power to a processor;
arranging a plurality of memory storage elements in the processor into a first configuration in which the memory storage elements form a chain;
loading data from a storage device into a first memory storage element in the chain; and
passing the data through the chain. - View Dependent Claims (19)
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20. A computer system comprising:
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a processor having a plurality of memory storage elements; and
interconnection elements, responsive to detecting which of normal or low power operation is being carried out by the processor, to interconnect said memory storage elements in a first configuration during normal operation of the processor and to connect the memory storage elements in a second configuration upon entry into said low-power mode of operation of the processor anda storage device coupled to exchange data with the processor;
a power supply connected to supply power to the processor during the normal operation and to withhold power from the processor during the low-power mode of operation. - View Dependent Claims (21, 22, 23)
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Specification