Turbo decoder with modified input for increased code word length and data rate

• US 6,715,120 B1
• Filed: 04/28/2000
• Issued: 03/30/2004
• Est. Priority Date: 04/30/1999
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Ross, John Anderson Fergus, Wodnicki, Robert Gideon, Van Stralen, Nick Andrew, Hladik, Stephen Michael, Itani, Abdallah Mahmoud
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/561,334
• Time in Patent Office: 1,432 Days
• Field of Search: 714/755, 714/780, 714/786, 714/794
• US Class Current: 714/755
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/3933 Decoding in probability domain
• CPC Class Codes: H03M 13/3972 using sliding window techniques or parallel windows

Abstract

A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data rate capability of the turbo decoder. Upon completion of any half iteration of the MAP decoding algorithm, the a posteriori bit probability estimates are provided to an interleave/de-interleave-and-convert-data function block wherein they are re-ordered, segmented, used to modify the original received data samples, and provided back to the respective turbo decoder modules as input data samples for the systematic bits. Decoding continues in this manner until a predetermined number of half iterations is performed, and data decisions are made on the final a posteriori estimates.

Claims

1. A turbo decoder system, comprising:

a plurality M of turbo decoder modules, each for decoding a maximum code word size corresponding to N information bits according to a MAP decoding algorithm;

interleave/de-interleave-and-convert-data (IDC) circuitry for receiving input data samples having an (M·

N)-bit block-length, the IDC circuitry segmenting the input data samples into M segments, the IDC having predetermined interleaver and de-interleaver definitions therein, each respective segment being provided to a respective turbo decoder module which provides as output a posteriori bit probabilities based on the respective segment of input data samples, the IDC circuitry re-ordering and modifying the input data samples based on the a posteriori bit probabilities, the IDC circuitry providing the re-ordered and modified data samples to the turbo decoder modules for a predetermined number of decoding iterations.

2. The system of claim 1 wherein the a posteriori bit probabilities are re-ordered according to the interleaver definition upon the end of odd-numbered half iterations and according to the de-interleaver definition upon the end of even-numbered half iterations.

3. The system of claim 1 wherein the interleave/de-interleave functions of the IDC circuitry occur before the convert data function.

4. The system of claim 1 wherein the interleave/de-interleave functions of the IDC circuitry occur after the convert data function.

5. A method for turbo decoding input data samples, each input data sample having an (M·

N)-bit block-length;

segmenting the input data samples into M segments, each respective segment being provided to a respective turbo decoder module which provides as outputs a posteriori bit probabilities based on the respective segment of input data samples;

re-ordering and modifying the input data samples based on the a posteriori bit probabilities for a predetermined number of decoding iterations;

the input data samples being re-ordered according to an interleaver definition upon odd-numbered half iterations and according to a de-interleaver definition upon even-numbered half iterations; and

making data decisions based on the final a posteriori bit probabilities.

6. The method of claim 5 wherein re-ordering occurs before modifying upon each half iteration.

7. The method of claim 5 wherein modifying occurs before re-ordering upon each half iteration.