Method of forming a surface coating layer within an opening within a body by atomic layer deposition
First Claim
1. A method of forming trench and channel, or tunnel, openings for an inductor comprising the following steps:
- (a) providing an insulating layer overlying a substrate;
(b) forming a patterned first silicon nitride sacrificial layer, for subsequent channel formation, over the insulating layer;
(c) providing a first dielectric layer, overlying said patterned first silicon nitride sacrificial layer;
(d) forming a patterned second silicon nitride sacrificial layer over the first dielectric layer;
(e) forming a second dielectric layer, over said patterned second silicon nitride sacrificial layer and planarizing the second dielectric layer, by chemical mechanical polishing;
(f) forming via openings in the second dielectric layer, by patterning and selectively removing regions of the second dielectric layer, by a reactive ion etch, stopping on the patterned second silicon nitride sacrificial layer, while exposing portions of the underlying first silicon nitride sacrificial layer;
(g) changing plasma etching chemistry to etch through exposed regions of the underlying second silicon nitride sacrificial layer, and while continuing to pattern the first dielectric layer, forming vertical channels of the inductor by reactive ion etching, stopping on the patterned first silicon nitride sacrificial layer;
(h) selectively wet etching away the underlying first and second silicon nitride sacrificial layers, thus forming both top and bottom horizontal channels or tunnels.
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Abstract
An improved new process for fabricating multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in semiconductors, for copper interconnects and inductors, as well as, in the field of bio-sensors for mini- or micro-columns in gas or liquid separation, gas/liquid chromatography, and in capillary separation techniques. In addition, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a type of damascene process, to form copper interconnects and inductors.
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Citations
28 Claims
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1. A method of forming trench and channel, or tunnel, openings for an inductor comprising the following steps:
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(a) providing an insulating layer overlying a substrate;
(b) forming a patterned first silicon nitride sacrificial layer, for subsequent channel formation, over the insulating layer;
(c) providing a first dielectric layer, overlying said patterned first silicon nitride sacrificial layer;
(d) forming a patterned second silicon nitride sacrificial layer over the first dielectric layer;
(e) forming a second dielectric layer, over said patterned second silicon nitride sacrificial layer and planarizing the second dielectric layer, by chemical mechanical polishing;
(f) forming via openings in the second dielectric layer, by patterning and selectively removing regions of the second dielectric layer, by a reactive ion etch, stopping on the patterned second silicon nitride sacrificial layer, while exposing portions of the underlying first silicon nitride sacrificial layer;
(g) changing plasma etching chemistry to etch through exposed regions of the underlying second silicon nitride sacrificial layer, and while continuing to pattern the first dielectric layer, forming vertical channels of the inductor by reactive ion etching, stopping on the patterned first silicon nitride sacrificial layer;
(h) selectively wet etching away the underlying first and second silicon nitride sacrificial layers, thus forming both top and bottom horizontal channels or tunnels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming trench and channel, or tunnel, openings and then coating the surface of trench and channel or tunnel, openings with a copper barrier layer and a copper seed layer, in the fabrication of interconnects and inductors, comprising the following steps:
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(a) providing an insulating layer overlying a substrate;
(b) forming a patterned first silicon nitride sacrificial layer, for subsequent channel formation, over the insulating layer;
(c) providing a first dielectric layer overlying said patterned first silicon-nitride sacrificial layer;
(d) forming a patterned second silicon nitride sacrificial layer over the first dielectric layer;
(e) forming a second dielectric layer over said patterned second silicon nitride and planarizing the second dielectric layer by chemical mechanical polishing;
(f) forming via openings in the second dielectric layer by patterning and selectively removing regions of the second dielectric layer by a reactive ion etch, stopping on the patterned second silicon nitride sacrificial layer, while exposing portions of underlying first silicon nitride sacrificial layer;
(g) changing plasma etching chemistry to etch through exposed regions of the underlying second silicon nitride sacrificial layer, and while continuing to pattern the first dielectric layer forming vertical channels of the inductors by reactive ion etching, stopping on the patterned first silicon nitride sacrificial layer;
(h) selectively wet etching away the underlying patterned first and second silicon nitride sacrificial layers, forming both top and bottom horizontal channel or tunnel openings;
(i) depositing said copper barrier layer coating both vertical channels and horizontal channels or tunnels in the first and second dielectric layers, by atomic layer deposition;
(j) depositing said copper seed layer overlying said copper barrier layer, by atomic layer deposition, thus coating the surface of trench and channel or tunnel, openings with said copper barrier layer and said copper seed layer, in the fabrication of interconnects and inductors. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of forming trench and channel, or tunnel openings and then coating the surface of trench and channel or tunnel openings with a copper barrier layer and a copper seed layer, filling the tunnel openings by electroless plating of copper, in the fabrication of interconnects and inductors, comprising the following steps:
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(a) providing an insulating layer overlying a substrate;
(b) forming a patterned first silicon nitride sacrificial layer, for subsequent channel formation, over the insulating layer;
(c) providing a first dielectric layer overlying said patterned first silicon nitride sacrificial layer;
(d) forming a patterned second silicon nitride sacrificial layer over the first dielectric layer;
(e) forming a second dielectric layer over said patterned second silicon nitride and planarizing the second dielectric layer by chemical mechanical polishing;
(f) forming via openings in the second dielectric layer by patterning and selectively removing regions of the second dielectric layer by a reactive ion etch, stopping on the second silicon nitride sacrificial layer, while exposing portions of the underlying first silicon nitride sacrificial layer;
(g) changing plasma etching chemistry to etch through exposed regions of the underlying second silicon nitride sacrificial layer, and while continuing to pattern the first dielectric layer forming vertical channels of the inductors by reactive ion etching, stopping on the first silicon nitride sacrificial layer;
(h) selectively wet etching away the underlying first and second silicon nitride sacrificial layers, forming both top and bottom horizontal channel or tunnel openings;
(i) depositing a bottom copper barrier layer, first barrier, coating both vertical channels and horizontal channels or tunnels in the first and second dielectric layers, by atomic layer deposition;
(j) depositing said copper seed layer overlying said bottom copper barrier layer, by atomic layer deposition, coating surface of trench and channel or tunnel openings with said bottom copper barrier layer and said copper seed layer;
(k) performing electroless copper plating copper on said copper seed layer filling trench and channel or tunnel openings with an excess of copper;
(l) removing said excess of copper and planarizing back the excess copper by chemical mechanical polishing;
(m) depositing a top blanket copper barrier layer, second barrier, thus completing the fabrication of inlaid copper interconnects and inductors. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification