Method for filling depressions on a semiconductor wafer

• US 6,716,720 B2
• Filed: 03/03/2003
• Issued: 04/06/2004
• Est. Priority Date: 03/02/2002
• Status: Expired due to Term

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Infineon Technologies AG
• Inventors: Efferenn, Dirk, Moll, Hans-Peter
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US10/378,244
• Publication Number:
  US 20030166327A1
• Time in Patent Office: 400 Days
• Field of Search: 438/424, 438/437, 438/697, 438/705, 438/FOR.103, 438/759, 438/FOR.267, 438/FOR.388
• US Class Current: 438/424
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

Claims

1. A method for filling a depression between two vertically adjoining semiconductor layers, the method which comprises:

forming two vertically adjoining semiconductor layers on a semiconductor wafer, the two semiconductor layers being made of different materials and an edge depression forming near a transition between the two semiconductor layers;

in a large-area manner, applying an essentially uniform covering layer having a predetermined layer thickness above the two semiconductor layers to cover the two semiconductor layers and the edge depression lying between the two semiconductor layers;

increasing a rate at which the covering layer can be subsequently removed by introducing a doping material into the covering layer essentially down to a depth corresponding to the layer thickness of the covering layer; and

removing the covering layer with the doping material such that undoped covering layer material remains in the edge depression.

2. The method according to claim 1, which comprises providing the covering layer as an electrically neutral material.

3. The method according to claim 1, which comprises using an electrically neutral material as the doping material.

4. The method according to claim 1, wherein the step of introducing the doping material into the covering layer loosens a structure of the covering layer.

5. The method according to claim 1, which comprises using material of one of the two semiconductor layers as material for the covering layer.

6. The method according to claim 1, which comprises performing the step of forming the two semiconductor layers by:

patterning a mask layer on the semiconductor wafer to define a trench region;

forming a trench in the semiconductor wafer;

in a large-area manner, applying an oxide layer to fill the trench;

removing the oxide layer to uncover the mask layer; and

removing the mask layer.

7. The method according to claim 6, wherein the step of applying the covering layer includes forming an oxide layer as the covering layer.

8. The method according to claim 7, which comprises using nitrogen as the doping material.

9. The method according to claim 8, wherein the oxide layer has a layer thickness of approximately 25 nm and the nitrogen is implanted with an energy of 8 keV.