Thin film semiconductor device containing polycrystalline Si—Ge alloy and method for producing thereof

• US 6,716,726 B2
• Filed: 10/22/2002
• Issued: 04/06/2004
• Est. Priority Date: 02/01/2001
• Status: Expired due to Term

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Shiba, Takeo, Hatano, Mutsuko, Park, Seong-Kee, Yamaguchi, Shinya
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Sarkar, Asok Kumar
• Application Number:
  US10/277,140
• Publication Number:
  US 20030049892A1
• Time in Patent Office: 532 Days
• Field of Search: 257/19, 257/347-354, 438/141, 438/142, 438/149, 438/150, 438/164, 438/166, 438/168, 438/172, 438/311, 438/312, 438/482-491, 438/586, 438/796, 438/798, 438/933
• US Class Current: 438/487
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

The present invention relates to a thin film transistor, in a low-temperature poly-Si thin film becoming an elemental material of the thin film transistor, an object of the invention is to provide the thin film transistor suitable for realizing an image display device having a high performance and a large area at low cost by realizing a poly-crystalline thin film having a crystal structure restraining current scattering in a grain boundary, lessening surface roughness, and capable of realizing high mobility even to a positive hole current.

The object described above is achieved by realizing a TFT with high mobility by restraining a current scattering factor in a grain boundary of crystal with an introduction of Ge into the poly-crystalline Si thin film and with a difference in ratios of Ge compositions between an interior grain of crystal and a grain boundary of crystal resulted from a phase separation involved in crystallization, and by restraining surface roughness using a difference in volumes in a crystal.

Claims

1. A method for producing a thin film transistor device comprising steps of:

(a) forming an amorphous Si_1-xGe_x layer of a film thickness of 10-100 nm on an insulator substrate in which a Ge concentration x is 0<

x<

1; and

(b) being subjected to a heat treatment for crystallizing the amorphous Si_1-xGe_x layer by an excimer laser with an energy density of 200-300 mJ/cm² and the pulse number of 1-50 by which the amorphous Si_1-xGe_x layer turns to a silicone-germanium poly-crystalline Si_1-xGe_x in which a Ge concentration x is 0<

x<

1, and a Ge concentration x in the poly-crystalline thin film is larger in a grain boundary than a portion where a Ge concentration in an interior crystal grain of the poly-crystalline thin film becomes a minimum value.

2. A method for producing a thin film transistor device as set forth in claim 1, wherein said step of heat treatment varies with the energy density as (180+T)˜

(200+T) mJ/cm² according to a film thickness when the film thickness of said amorphous Si_1-xGe_x layer is set as T nm.

3. A method for producing a thin film transistor device according to claim 2, wherein the Ge concentration x in the interior crystal grain of the poly-crystalline thin film is 0<

x<

0.1 and the Ge concentration x in the grain boundary of the poly-crystalline thin film is 0.3≦

x<

1.

4. A method for producing a thin film transistor device according to claim 1, wherein the Ge concentration x in the interior crystal grain of the poly-crystalline thin film is 0<

x≦

1.

5. A method of forming a transistor device comprising:

(a) forming an amorphous Si_1-xGe_x layer having a thickness of 10-100 nm on an insulator substrate in which a Ge concentration x is 0<

x<

1; and

(b) heat treating the amorphous Si_1-xGe_x layer using an excimer laser with an energy density of 200-300 mJ/cm² and a pulse number of 1-50 by which the amorphous Si_1-xGe_x layer turns to a silicone-germanium poly-crystalline Si_1-xGe_x in which a Ge concentration x is 0<

x<

1, and a Ge concentration x in the poly-crystalline thin film is larger in a grain boundary than a portion where a Ge concentration in an interior crystal grain of the poly-crystalline thin film becomes a minimum value.

6. A method of forming a transistor device as set forth in claim 5, wherein said heat treatment varies with the energy density as (180+T)˜

(200+T) mJ/cm² according to a film thickness when the film thickness of said amorphous Si_1-xGe_x layer is set as T nm.

7. A method of forming a transistor device as set forth in claim 5, wherein the Ge concentration x in the interior crystal grain of the poly-crystalline is 0<

x≦

1.

8. A method of forming a transistor device as set forth in claim 5, wherein the Ge concentration x in the interior crystal grain of the poly-crystalline thin film is 0<

x≦

0.1 and the Ge concentration x in the grain boundary of the poly-crystalline thin film is 0.3≦

x<

1.